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[Embeded-SCM Develop] verilog_code

Description: 這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
Platform: | Size: 170444 | Author: ㄚ福 | Hits:

[Embeded-SCM Develop] verilog_code

Description: 這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
Platform: | Size: 169984 | Author: ㄚ福 | Hits:

[VHDL-FPGA-Verilog] DEMO22

Description: ＶＨＤＬ源程序，ＭＡＸＰＬＵＳ　环境下运行，电梯控制系统-VHDL source code, under Operation Converter, elevator control system
Platform: | Size: 598016 | Author: liu | Hits:

[VHDL-FPGA-Verilog] I2S

Description: 这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
Platform: | Size: 1583104 | Author: 孙浩 | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[VHDL-FPGA-Verilog] bunchcombinechange

Description: Verilog源代码,实现串并转换，学Verilog的不错的基本例程-Verilog source code, realize SERDES, learning Verilog good basic routines
Platform: | Size: 114688 | Author: 3060421006 | Hits:

[VHDL-FPGA-Verilog] 76_PID

Description: 一个非常好的电机转速控制器VHDL源代码设计-A very good motor speed controller VHDL design source code
Platform: | Size: 2048 | Author: linew | Hits:

[Software Engineering] labQ2

Description: Source codes for verilog fifo for spartan 3
Platform: | Size: 252928 | Author: Krishna | Hits:

[VHDL-FPGA-Verilog] minimigJ_source_04_08_2008

Description: Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
Platform: | Size: 195584 | Author: lihard | Hits:

[Other Games] Source_minimig_DE1_DE2_12e_new

Description: Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-de1/de2 used on the de1 and de2 fpga boards.
Platform: | Size: 306176 | Author: lihard | Hits:

[Other Games] snapshot_ver1.26

Description: Verilog, VHDL, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version c-one used on the c-one fpga board.
Platform: | Size: 1065984 | Author: lihard | Hits:

[VHDL-FPGA-Verilog] sdram32

Description: DDR SDRAM source verilog source codes
Platform: | Size: 25600 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] VerilogLabSource

Description: Verilog Lab Source Codes
Platform: | Size: 2048 | Author: omid | Hits:

[VHDL-FPGA-Verilog] syn-fifo-verilog

Description: 用verilog语言写的同步FIFO设计源代码。-The source codes for syn-fifo using verilog language.
Platform: | Size: 100352 | Author: runxin218 | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] 5-verilog-programs

Description: the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
Platform: | Size: 5120 | Author: Srinath | Hits:

[VHDL-FPGA-Verilog] Codes-and-Reports

Description: Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
Platform: | Size: 10629120 | Author: imranity | Hits:

[VHDL-FPGA-Verilog] verilog-source-codes

Description: the attached programs are source codes of 4-bit ring counter, 16x1 mux, 8x3 priority encoder, 4x16 decoder, full subtractor using two half subtractors
Platform: | Size: 2048 | Author: apparao | Hits:

[Com Port] 12spi.tar

Description: SPIverilog代码,属于SOC的子模块，SOC片上系统的一个子模块-SPI verilog source codes
Platform: | Size: 5120 | Author: flychan | Hits:
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