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[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: verilog 硬件平方根算法 采用与笔算平方根一样的算法-Verilog hardware and written calculation algorithm uses the square root of the square root of the same algorithm
Platform: | Size: 17408 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] HDL_design

Description:
Platform: | Size: 663552 | Author: Ning Zheng | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: This zip file contains the verilog source code for square root calculation and its test bench
Platform: | Size: 2048 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG
Platform: | Size: 1024 | Author: 神气 | Hits:

[VHDL-FPGA-Verilog] square-root

Description: Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware description language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation available are introduced. This thesis include the design of square root machine which is based on the EasyFPGA030 ,as well as the details of the design process Verilog language use and achieve results.
Platform: | Size: 905216 | Author: stella | Hits:

[VHDL-FPGA-Verilog] sqrt_for_single_float_point

Description: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Platform: | Size: 5120 | Author: 楚艳超 | Hits:

[VHDL-FPGA-Verilog] SQRT

Description: 用verilog代码编写的求整数平方根的FPGA工程。-Verilog code written request with the integer square root of the FPGA project.
Platform: | Size: 237568 | Author: 袁媛 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG description of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
Platform: | Size: 1024 | Author: Solomon | Hits:

[Windows Develop] cordic

Description: verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
Platform: | Size: 1024 | Author: 刘大远 | Hits:

[Other] adder

Description: 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral description, ripple carry, the square root of the carry , with a simple testbench
Platform: | Size: 3072 | Author: D | Hits:

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