Search - verilog switch

[Static control] clock2001

Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Platform: | Size: 1024 | Author: dandan | Hits:

[Multimedia program] H263video

Description: H.263的视频压缩算法和测试程序，可以对原始图像和转码后的图像进行比较。开发环境为vc6.0。-H.263 video compression algorithm and testing procedures, the original image and switch codes after the images were compared. Development Environment for vc6.0.
Platform: | Size: 362496 | Author: lh | Hits:

[Other] chinese_VerilogHDL

Description: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模，想学习的这个资料对你有用。-Verilog HDL is a hardware description language, for the algorithm level, gate-level to switch-level abstract design of the multiple levels of system modeling, want to study this information be useful to you.
Platform: | Size: 32768 | Author: 刘斐 | Hits:

[VHDL-FPGA-Verilog] time_run

Description: verilog描述年月日，小时分秒的显示，2000~2099年的万历年循环用set控制，设置状态，按一下改变一个设置，正常显示时，按set进入小时设置，依次是分钟，年，月，天（天设置带懂周变换）在设置状态，按一下ADJ，加一下，按cf就减1，同步修改显示；设置状态下，按mode键或是60秒无按键，推出设置状态，返回正常显示正常显示是，按ADJ，进行24，12小时显示切换，带AM_PM显示-Verilog description of date, hours minutes and seconds display, from 2000 to 2099 million in the calendar year cycle with set control, set the status, click to change a setting, the normal display, press set to enter the hour set, followed by minute, year, month , days (days of week settings to understand transformation zone) in the set status, click the ADJ, plus some, by cf on by 1, modify the display simultaneously settings, press mode button or no button for 60 seconds, set to launch a state, return normal display is the normal display, press ADJ, switch to 24,12-hour show, with shows AM_PM
Platform: | Size: 4096 | Author: 申刚 | Hits:

[assembly language] EEPROMpresentation

Description: 利用拨码开关为可编程器件输入读写命令和相应的地址、数据，8051读入可编程器件设定的命令字并根据可编程器件的设置进行读写操作，读出来的数据通过P0输出给可编程器件，并由可编程器件控制七段数码管显示。(Verilog+单片机)-DIP switch for the use of programmable devices to read and write command input and the corresponding address, data, read into the programmable device 8051 set the word order and in accordance with programmable device settings for read and write operations, read out the data through P0 output to the programmable device, programmable device controlled by the Seven-Segment LED display. (Verilog+ Singlechip)
Platform: | Size: 3072 | Author: 辛颖 | Hits:

[VHDL-FPGA-Verilog] lift_code_verilog

Description: 实现一个4层楼的单电梯控制系统。门可以自动开关也可以手动开关。代码可综合，无多驱动现象。-Realize a 4-story single-elevator control system. Door can automatically switch can also manually switch. Code can be integrated, no more than drive the phenomenon.
Platform: | Size: 3072 | Author: 幻婳 | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[SCM] 16bit_display8bitLED

Description: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results.
Platform: | Size: 7168 | Author: 王媛媛 | Hits:

[Other] Verilog-HDL

Description: Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。-Verilog HDL is a hardware description language, for from the algorithm level, gate-level to switch-level abstract design of a variety of digital system-level modeling. Modeling of digital systems was the complexity of the object can range from simple door and integrity of electronic digital systems. Digital systems can be described at different levels and in the same explicit description for time series modeling.
Platform: | Size: 4169728 | Author: 成龙 | Hits:

[File Format] SDH

Description: FPGA的应用，数字交叉连接矩阵的应用，VERILOG的一些应用等-FPGA applications, the application of digital cross-connect matrix, VERILOG some of the applications
Platform: | Size: 707584 | Author: 辛晨 | Hits:

[VHDL-FPGA-Verilog] goip

Description: This application is about xinlinx fpga. initialize the gpio,led,switch and others in the college project board. If you are a novice, this application will help you shorten the learning time.
Platform: | Size: 4717568 | Author: sinong | Hits:

[Books] VerilogHDL_

Description: Verilog HDL 入门教程 Verilog HDL 是一种硬件描述语言，用于从算法级、RTL级、门级到开关级的多种抽象设计层次的数字系统建模。被建模的数字系统对象的复杂性可介于简单的门级和完整的电子数字系统之间。数字系统可按层次描述。-Introduction to Verilog HDL tutorials Verilog HDL is a hardware description language, used from the algorithm level, RTL-level, gate-level to switch level design of a variety of abstraction levels of digital system modeling. Modeling of digital systems is the complexity of an object can range from simple gate-level and complete electronic digital systems. Level description of digital systems can.
Platform: | Size: 263168 | Author: 孙 | Hits:

[VHDL-FPGA-Verilog] SwitchLed

Description: FPGA入门程序。适合编程初学者的学习。由开关控制LED灯的亮灭。ISE集成开发环境。Verilog HDL语言编写-FPGA entry procedures. Programming for beginners to learn. LED lights from the light switch control off. ISE Integrated Development Environment. Language Verilog HDL
Platform: | Size: 244736 | Author: 李海波 | Hits:

[VHDL-FPGA-Verilog] T1_SW_PB

Description: 这个程序是用来测试拨码开关与按键开关的，当按下按键开关时，相应的led会点亮，同理打开拨码开关相应的led也会点亮-This procedure is used to test the DIP switch and key switch, key switch, when pressed, the corresponding led will light, compassion to open DIP switch corresponding led will light up
Platform: | Size: 113664 | Author: shi | Hits:

[VHDL-FPGA-Verilog] switch

Description: 该模块是一个基于verilog的脉冲触发高低电平保持的模块，同时包含了消抖的功能。主要是针对现今许多开发板上开关是弹簧式的手按下去为低电平，手一松就变成了高电平。只要按一次松开后，模块就能自动输出一个低电平。（板子上的开关正常情况为高电平）同时消抖部分在输入clk为50Mhz的时候可以延迟21ms来判断是否为开关按下-The module is based on verilog pulsed high-low to keep the trigger module includes both debounce function. Mainly on the development board for many of today' s switches are spring-loaded hand down low by the hand of a song becomes a high level. As long as the press release, the module will automatically output a low level. (Switch on the board is high normal) while the input debounce clk is 50Mhz part when you can delay 21ms to determine whether the switch is pressed
Platform: | Size: 1024 | Author: 刘卫菠 | Hits:

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[Static control] clock2001

[Multimedia program] H263video

[Other] chinese_VerilogHDL

[VHDL-FPGA-Verilog] time_run

[assembly language] EEPROMpresentation

[VHDL-FPGA-Verilog] lift_code_verilog

[Other] Verilog

[VHDL-FPGA-Verilog] VerilogHDL_code

[SCM] 16bit_display8bitLED

[Other] Verilog-HDL

[File Format] SDH

[VHDL-FPGA-Verilog] goip

[Books] VerilogHDL_

[VHDL-FPGA-Verilog] SwitchLed

[VHDL-FPGA-Verilog] T1_SW_PB

[VHDL-FPGA-Verilog] switch

[VHDL-FPGA-Verilog] switch

[VHDL-FPGA-Verilog] switch_system_verilog

[VHDL-FPGA-Verilog] switch

[VHDL-FPGA-Verilog] switch

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