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Description: 基于Verilog-HDL的硬件电路的实现
9.7 步进电机的控制
9.7.1 步进电机驱动的逻辑符号
9.7.2 步进电机驱动的时序图
9.7.3 步进电机驱动的逻辑框图
9.7.4 计数模块的设计与实现
9.7.5 译码模块的设计与实现
9.7.6 步进电机驱动的Verilog-HDL描述
9.7.7 编译指令-\"宏替换`define\"的使用方法
9.7.8 编译指令-\"时间尺度`timescale\"的使用方法
9.7.9 系统任务-\"$finish\"的使用方法
9.7.10 步进电机驱动的硬件实现
-based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology -- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module Design and Implementation 9.7.5 decoding module design and Implementation 9.7.6 stepper motor driven Verilog-HDL Compiler means locale 9.7.7 Description Order - "macro substitution` define "the use 9.7.8 compiler directives -" The time scale `tim escale "use 9.7.9 system tasks -" $ finish "to use 9.7.10 stepper motor drive hardware
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Size: 2523 |
Author: 宁宁 |
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Description: 基于Verilog-HDL的硬件电路的实现
9.7 步进电机的控制
9.7.1 步进电机驱动的逻辑符号
9.7.2 步进电机驱动的时序图
9.7.3 步进电机驱动的逻辑框图
9.7.4 计数模块的设计与实现
9.7.5 译码模块的设计与实现
9.7.6 步进电机驱动的Verilog-HDL描述
9.7.7 编译指令-"宏替换`define"的使用方法
9.7.8 编译指令-"时间尺度`timescale"的使用方法
9.7.9 系统任务-"$finish"的使用方法
9.7.10 步进电机驱动的硬件实现
-based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology-- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module Design and Implementation 9.7.5 decoding module design and Implementation 9.7.6 stepper motor driven Verilog-HDL Compiler means locale 9.7.7 Description Order- "macro substitution` define "the use 9.7.8 compiler directives-" The time scale `tim escale "use 9.7.9 system tasks-" $ finish "to use 9.7.10 stepper motor drive hardware
Platform: |
Size: 2048 |
Author: 宁宁 |
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Description: ep2c5 实现 定时器
verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: |
Size: 497664 |
Author: lizhuodong |
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