Search - verilog u

[Other resource] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5599 | Author: 李文文 | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5599 | Author: richman | Hits:

[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[Algorithm] U-rand(0-100)

Description: 0-100伪随机数发生函数代码，希望程序能用得上，-0-100 pseudo-random number generating function codes, procedures can hope that none?
Platform: | Size: 1024 | Author: 陈波 | Hits:

Description: verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过-verilog achieve, UDP asynchronous reset with a description of the fringe is triggered D flip-flop, test test pass
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] pcit32_verilog_lattice

Description: 这个我也太清楚是什么反正师兄们说有用发大家-I am also very clear that what is useful anyway, say senior U.S. fa
Platform: | Size: 430080 | Author: wang | Hits:

[File Format] hash

Description: 主要关于hash算法的一些资料，个人觉得比较好，与大家共享-Hash algorithm is mainly concerned with some of the information, individuals feel better, and the U.S. share
Platform: | Size: 4294656 | Author: 张晓梅 | Hits:

[VHDL-FPGA-Verilog] alaw_mulaw

Description: 这是一个量化编码当中关于A律和u律压缩和扩展的源程序，程序由VerilogHDL语言编写，算法在Modelsim上进行仿真过-This is a quantization coding of them on the A law and u law compression and expansion of the source code, the program by VerilogHDL languages, algorithms in the ModelSim simulation have been carried out
Platform: | Size: 62464 | Author: 刘柳 | Hits:

[VHDL-FPGA-Verilog] DDSverilogsource

Description: DDS的VERILOG原代码，请大家多支持-DDS of the Verilog source code, please support the U.S. more than
Platform: | Size: 3072 | Author: 屈开 | Hits:

[VHDL-FPGA-Verilog] Verilog[lattice]

Description: 这是一有很好价值的verilog教程,本人就因此获意非浅,再次贡献给大家,希望大家有所帮助.-This is a very good value Verilog tutorial, I am going to be intended to greatly therefore, contribute to the U.S. again, I hope everybody help.
Platform: | Size: 143360 | Author: ixia | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 有例程和VERILONG语言的描述,可能对初学者有用.如果谁有好的VERILONG自己写的程序,请大家上传一些,借鉴一下-Have routines and VERILONG description language may be useful for beginners. If good VERILONG who write their own procedures, please upload some U.S. learn from you
Platform: | Size: 113664 | Author: 李 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 这是一个用verilog语言设计的数字频率及的源代码，上传一下，供大家研究 -This is a design using Verilog language and the digital frequency of the source code, upload click for U.S. research
Platform: | Size: 427008 | Author: bbbbbbbb | Hits:

[Windows Develop] key

Description: 使用verilog实现的4x4的键盘，但是把延时程序去掉了，可以给大家参考-Verilog realize the use of the 4x4 keyboard, but to delay proceedings removed, you can refer to the U.S.
Platform: | Size: 199680 | Author: wphyl | Hits:

[Other] u-uart

Description: UART verilog TX/RX OpenCores share
Platform: | Size: 5120 | Author: richman | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[Compress-Decompress algrithms] DDC

Description: matlab与synplify DSP AE相结合的DDC实例，希望对大家有所帮助-matlab and synplify DSP AE combining DDC example, in the hope that U.S. help
Platform: | Size: 187392 | Author: luocaijin | Hits:

[VHDL-FPGA-Verilog] usb_FPGA

Description: 实现USB接口功能的VHDL和verilog完整源代码-Implementation USB interface functions of the VHDL and Verilog source code integrity
Platform: | Size: 260096 | Author: liang | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[VHDL-FPGA-Verilog] Verilog_UDP

Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Platform: | Size: 125952 | Author: 龙也 | Hits:

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[Other resource] u-uart

[Other] u-uart

[VHDL-FPGA-Verilog] u-uart

[Algorithm] U-rand(0-100)

[Embeded-SCM Develop] dff_UDP

[VHDL-FPGA-Verilog] pcit32_verilog_lattice

[File Format] hash

[VHDL-FPGA-Verilog] alaw_mulaw

[VHDL-FPGA-Verilog] DDSverilogsource

[VHDL-FPGA-Verilog] Verilog[lattice]

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] verilog

[Windows Develop] key

[Other] u-uart

[Algorithm] multiply

[Compress-Decompress algrithms] DDC

[VHDL-FPGA-Verilog] usb_FPGA

[Other] Verilog

[VHDL-FPGA-Verilog] Verilog_UDP

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