Search - verlog hdl

[Other resource] calendar_clock

Description: 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
Platform: | Size: 1785632 | Author: zz | Hits:

[Other resource] VERlog

Description: 不错的VHDL讲义?淮淼腣HDL讲义-good VHDL overhead good VHDL overhead
Platform: | Size: 235200 | Author: 刘刚 | Hits:

[Other resource] adder

Description: 此程序为用VERLOG HDL编写的一个完整的3位加法器。
Platform: | Size: 1498 | Author: liuwei | Hits:

[Other resource] an487_design_example

Description: 用verlog hdl开发的SPI 的源码
Platform: | Size: 603423 | Author: zhiqiang | Hits:

[Other resource] vhdl

Description: 非常经典的verlog hdl 语言学习教程及开发程序开发事例
Platform: | Size: 3170877 | Author: tieyu | Hits:

[Other resource] BLDCM

Description: verlog hdl无刷电机控制程序,已在modelsim仿真
Platform: | Size: 200300 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] calendar_clock

Description: 用verlog HDL写的电子日历,可以显示年,月,日和时间,具有闹铃的功能-using HDL to write electronic calendar, it shows the year, month, day and time, with alarm function
Platform: | Size: 1785856 | Author: zz | Hits:

[Other] VERlog

Description: 不错的VHDL讲义?淮淼腣HDL讲义-good VHDL overhead good VHDL overhead
Platform: | Size: 234496 | Author: | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 此程序为用VERLOG HDL编写的一个完整的3位加法器。-This procedure for VERLOG HDL prepared with a full adder 3.
Platform: | Size: 1024 | Author: liuwei | Hits:

[VHDL-FPGA-Verilog] an487_design_example

Description: 用verlog hdl开发的SPI 的源码-Verlog hdl use the source code developed by SPI
Platform: | Size: 603136 | Author: zhiqiang | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 非常经典的verlog hdl 语言学习教程及开发程序开发事例-Very classic verlog hdl Language Learning Course and development of procedures for the development of case
Platform: | Size: 3170304 | Author: | Hits:

[VHDL-FPGA-Verilog] BLDCM

Description: verlog hdl无刷电机控制程序,已在modelsim仿真-verlog hdl brushless motor control procedures have been in ModelSim Simulation
Platform: | Size: 199680 | Author: 李军 | Hits:

[SCM] sgs32

Description: Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable duty cycle. See readme.doc. Here only provide a source module that contains the top-level sub-modules sgs32.v settings dds.v and pll module altp.v and waveform-driven document
Platform: | Size: 59392 | Author: TTHR | Hits:

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[Other resource] calendar_clock

[Other resource] VERlog

[Other resource] adder

[Other resource] an487_design_example

[Other resource] vhdl

[Other resource] BLDCM

[VHDL-FPGA-Verilog] calendar_clock

[Other] VERlog

[VHDL-FPGA-Verilog] uartverlog

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] an487_design_example

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] BLDCM

[SCM] sgs32

[VHDL-FPGA-Verilog] fir

[Communication-Mobile] cordic.tar

[VHDL-FPGA-Verilog] clock_digital

[Other] Howtowritestatemachine

[VHDL-FPGA-Verilog] adder

[VHDL-FPGA-Verilog] adder8

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