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[Other resource] Shifters_vhdl

Description: -- Title : Barrel Shifter (Pure combinational) -- This VHDL design file is an open design you can redistribute it and/or -- modify it and/or implement it after contacting the author -- You can check the draft license at --- Title : Barrel Shifter (Pure combinational) -- This VH DL design file is an open design you can redistri bute it and / or -- modify it and / or implement it a fter contacting the author -- You can check the d raft license at
Platform: | Size: 2025 | Author: 陈朋 | Hits:

[OpenGL program] bioviewer-0.0.21

Description: A C++/SDL/OpenGL player for the Biovision .bvh file format, which stores hierarchical motion data commonly originating from motion capture hardware. Support for the Kaydara .fbx format (a general 3D interchange format) is planned.-A C / SDL / OpenGL volunteered for the player. B vh file format, hierarchical motion which stores data commonl y originating from motion capture hardware. Su pport for the Kaydara. fbx format (a general 3D i nterchange format) is planned.
Platform: | Size: 784035 | Author: brotherfor | Hits:

[Other resource] RAM_VHDL_34

Description: RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL description RAM's VHDL description RAM's VH DL described in VHDL's RAM
Platform: | Size: 5418 | Author: Nicholas | Hits:

[Other resource] sdgshjd

Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ... -Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar] - 4 division of vhdl source [vh dl example. rar] - highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
Platform: | Size: 838 | Author: 张瑞 | Hits:

[Other resource] vh

Description: 有用的VHDL源代码-useful VHDL source code
Platform: | Size: 590903 | Author: 王新 | Hits:

[SourceCode] vh-20mr

Description:
Platform: | Size: 1426 | Author: zhaojun81@163.com | Hits:

[VHDL-FPGA-Verilog] FFT的VHDL源代码

Description: FFT的VHDL源代码-fft vhdl source code
Platform: | Size: 29696 | Author: 阿林 | Hits:

[VHDL-FPGA-Verilog] pwm

Description:
Platform: | Size: 214016 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] vh

Description: 有用的VHDL源代码-useful VHDL source code
Platform: | Size: 590848 | Author: 王新 | Hits:

[VHDL-FPGA-Verilog] vgaout

Description: VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
Platform: | Size: 7168 | Author: 余飞 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 altera提供-VHDL

Description: I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
Platform: | Size: 1639424 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] codestream

Description: 设计一个模块，从一个窜行数据流里检测出码流“11100”，这个模块包括reset,clk,datain及输出端pmatch-design a module from a trip data flow channeling Lane detected bitstream "11100", this module includes reset, clk, datain and output pmatch
Platform: | Size: 8192 | Author: 许嘉璐 | Hits:

[VHDL-FPGA-Verilog] richic_vga_top

Description: 有关 VHDL进行VGA显示的源程序，请大家好好参考-VHDL for the VGA display the source code, please make reference to
Platform: | Size: 27648 | Author: 111 | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[VHDL-FPGA-Verilog] vhdl_vga_kb

Description: VHDL的显示驱动程序，VHDL的PS2键盘驱动程序-VHDL display drivers, VHDL PS2 Keyboard Driver
Platform: | Size: 3072 | Author: 张明凯 | Hits:

[VHDL-FPGA-Verilog] (AMI)vhdl设计实例

Description: 这是一本介绍VHDL编成的教材，是一本实例，内有很多简单的复杂的源代码，使编程初学者的绝好工具-This is a VHDL introduced into the materials is an example, there are a lot of simple and complex source code, giving developers an excellent tool for beginners
Platform: | Size: 168960 | Author: AKXIAOHAI77 | Hits:

[VHDL-FPGA-Verilog] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 1024 | Author: 罗兵武 | Hits:

[VHDL-FPGA-Verilog] Example-2-1

Description: 这些是verilog的开发实例,仅供参考.实例1-These are examples of the development of Verilog, for reference purposes only. Example 1
Platform: | Size: 113664 | Author: john | Hits:

[VHDL-FPGA-Verilog] 12864lcd_vhdl

Description: 12864图形点阵液晶驱动vhdl程序，用ise综合-12864 graphics dot-matrix LCD driver VHDL program, and ideally integrated
Platform: | Size: 9423872 | Author: 赵晗 | Hits:
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