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[VHDL-FPGA-Verilog] Hello

Description: DE2板上的hello程序,实现在8个七段译码器上循环显示hello-err
Platform: | Size: 281600 | Author: 罗杰 | Hits:

[VHDL-FPGA-Verilog] LCD-hello

Description: VHDL syntax hello world for LCD written in VHDL MAXII evaluation board EPM1270F256C5
Platform: | Size: 1024 | Author: soroush | Hits:

[VHDL-FPGA-Verilog] HelloLED

Description: nios下实现helloled灯点亮 用vhdl语言编写 quartus环境实现-nios achieve helloled lamp lit environment with the vhdl language quartus to achieve
Platform: | Size: 3974144 | Author: PETER | Hits:

[VHDL-FPGA-Verilog] hello

Description: VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。-VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.
Platform: | Size: 1024 | Author: chunyu | Hits:

[VHDL-FPGA-Verilog] hello1

Description: 循环显示hello的vhdl程序，很实用哦，我们都试过-Hello, vhdl program cycle shows, it is practical Oh, we have tried
Platform: | Size: 1024 | Author: yuan | Hits:

[VHDL-FPGA-Verilog] hello-world

Description: VHDL CODE FOR DISPLAYING " HAPPY WORLD " ON XILINX SPARTAN 3 E FPGA BOARD
Platform: | Size: 9216 | Author: akki | Hits:

[VHDL-FPGA-Verilog] vhdl--example

Description: hello iam a coding word for you to doing vhdl h-hello iam a coding word for you to doing vhdl hoo
Platform: | Size: 11264 | Author: hello | Hits:

[VHDL-FPGA-Verilog] lcd_controller

Description: 本程序用VHDL语言实现LCD显示“hello，world”的功能，适用于ISE软件-This program with VHDL language LCD display " hello, world" functionality for ISE software
Platform: | Size: 1024 | Author: djy | Hits:

[VHDL-FPGA-Verilog] lab0-part4

Description: FPGA，ＶＨＤＬ，入门程序，可以在ＬＥＤ上面显示ｈｅｌｌｏ-FPGA, VHDL, and entry procedures, the LED above the display hello
Platform: | Size: 267264 | Author: lindamagic | Hits:

[Other] hello_world.vhdl

Description: A "Hello world" program is a computer program that outputs "Hello, world" on a display device. Because it is typically one of the simplest programs possible in most programming languages, it is by tradition often used to illustrate to beginners the most basic syntax of a programming language. It is also used to verify that a language or system is operating correctly.
Platform: | Size: 1024 | Author: iman | Hits:

[VHDL-FPGA-Verilog] DIVIDER

Description: 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is based on VHDL language of M bit by bit N divider. Where M/N, quotient M bits, the remainder is N bits. In Moim design verification and validation. Compression bag has a divider source files and testbench. May join the project, direct testing. I tests are error-free. After downloading Zunjia willing, positive comments, in order to facilitate mutual exchanges and learning. O (∩_∩) O Thank you. May 7, 2015 in Finland, Turku.
Platform: | Size: 2048 | Author: ljt | Hits:

[VHDL-FPGA-Verilog] lcd

Description: copy of hello word on FPGA
Platform: | Size: 190464 | Author: kentucky | Hits:

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