Search - vhdl sdh

[Other resource] Y312448

Description: 基于VHDL的SDH专用芯片的TOP-DOWN设计，内有全套源码以及图片，内容详尽，绝对真实可靠！
Platform: | Size: 2607300 | Author: 殷彦伟 | Hits:

Description: 帧同步检测源码，包括同步跟踪模块，fifo,分频模块，还有系统的测试平台-frame synchronization source detection, including synchronous tracking module, fifo, frequency module, and system test platform
Platform: | Size: 6144 | Author: liu | Hits:

[VHDL-FPGA-Verilog] Y312448

Description: 基于VHDL的SDH专用芯片的TOP-DOWN设计，内有全套源码以及图片，内容详尽，绝对真实可靠！-VHDL based on the SDH ASIC Design TOP-DOWN, which has a full set of source code, as well as pictures, and detailed, reliable and absolutely true!
Platform: | Size: 2607104 | Author: 殷彦伟 | Hits:

[VHDL-FPGA-Verilog] k21test

Description: 只需要FPGA两个通用管脚，就可以实现FPGA与PC机进行以太网通信！！如果你有ALTERA_DE1的开发板，可以直接下再看效果，用其他板子就要重新分配一下管脚，推荐使用电流输出。-Only two general-purpose FPGA pins, you can realize FPGA and Ethernet PC machine! ! If you have ALTERA_DE1 development board, you can look under the direct effect, with other board you will need to reconsider the distribution of pins, recommended the use of current output.
Platform: | Size: 880640 | Author: 245680 | Hits:

[Windows Develop] sdh

Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中，前9列为开销字节，它包含了很多重要的信息，本程序为SDH开销的接收处理，查找帧头，分频，勤务话字节E1异步fifo。可拆为三段源代码，不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived
Platform: | Size: 6144 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] 32ET_source

Description: 32时隙的VHDL源代码在开发E1 2M线路的时候非常有用-32 slot of the VHDL source code in the development of E1 2M lines is very useful when
Platform: | Size: 1024 | Author: 王鹏 | Hits:

[ActiveX/DCOM/ATL] sysfp

Description: 完成从SDH　telecom bus的38Mhz*4系统时钟和复帧提取出SDH的telecom bus的C1j1,spe,au指针　，H4位置等SDH帧结构-SDH telecom bus from 38Mhz* 4 the system clock and rehabilitation SDH frame to extract the telecom bus of C1j1, spe, au pointer, H4 location SDH frame structure
Platform: | Size: 1024 | Author: leon | Hits:

[Other] sdh

Description: 从sdh数据流中找到相应的帧，并将其帧头按照另一码率输出。-From the SDH data stream to find the corresponding frame, and another header in accordance with the output bit-rate.
Platform: | Size: 8192 | Author: 杨春 | Hits:

[Windows Develop] SDH

Description: 他是一个SDH上行代码，有八个模块组成的，能够传输以太网的数据 -He is an SDH uplink code, there is composed of eight modules, Ethernet can transmit data
Platform: | Size: 6144 | Author: 丁勇良 | Hits:

[VHDL-FPGA-Verilog] SDHAnalysis

Description: 光纤通信中的SDH数据帧解析及提取的VHDL实现源代码，共包含帧同步、E1及F1码流提取、DCC1码流提取、帧头开销串行输出四个主要模块-SDH fiber-optic communication data frame analysis and retrieval implementation of VHDL source code, include the frame synchronization, E1 and F1 stream extraction, DCC1 stream extraction, header overhead serial output four main modules
Platform: | Size: 31744 | Author: 张晓彬 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Other] FaultManag

Description: SDH Fault manangement
Platform: | Size: 411648 | Author: bhushan_bsk | Hits:

[VHDL-FPGA-Verilog] rzn725SDH

Description: 一个关于SDH中TU-12解帧的VHDL代码-On the SDH in a solution of TU-12 frame VHDL code for
Platform: | Size: 1698816 | Author: liyuan | Hits:

[VHDL-FPGA-Verilog] sdh1

Description: 本段代码是关于SDH帧的操作的一段VHDL的代码。主要需求为两部分： 1. 从连续传输的SDH字节流中找出帧头。 2. 从SDH字节流中，提取F1字节，并按照要求输出。-This section of code is on the operation of a SDH frame VHDL code. Two main needs: 1. From the continuous transmission of SDH byte stream to find the frame header. 2. SDH bytes from the stream, extract F1 bytes and the requested output.
Platform: | Size: 1024 | Author: mao | Hits:

[VHDL-FPGA-Verilog] SDH

Description: SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟） -Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
Platform: | Size: 2048 | Author: 刘镇宇 | Hits:

[VHDL-FPGA-Verilog] SDH_module

Description: SDH帧同步头的检测，并提取其中的语音信息的模块设计-SDH frame sync detection, and extract audio information module design
Platform: | Size: 353280 | Author: 雷伟林 | Hits:

[VHDL-FPGA-Verilog] code

Description: VHDL实现的LAPS协议实现的（LAPS：Link Access Procedure-SDH（SDH 上的链路接入规程））。包括发送机和接收机的程序-VHDL implementation of LAPS protocol implementation (LAPS: Link Access Procedure-SDH (SDH Link Access Procedure on)). Including procedures for transmitter and receiver
Platform: | Size: 5120 | Author: 王侃 | Hits:

[VHDL-FPGA-Verilog] VHDL_SDH

Description: 现代光纤通信SDH的VHDL源码，实现SDH开销的接收处理。-VHDL source code of modern fiber-optic communication SDH the SDH overhead of receiving and processing.
Platform: | Size: 57344 | Author: 张雷 | Hits:

[VHDL-FPGA-Verilog] SDH

Description: SDH vhdl实现-SDH VHDL
Platform: | Size: 175104 | Author: real | Hits:

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[Other resource] Y312448

[VHDL-FPGA-Verilog] sdh

[VHDL-FPGA-Verilog] Y312448

[VHDL-FPGA-Verilog] k21test

[Windows Develop] sdh

[VHDL-FPGA-Verilog] 32ET_source

[ActiveX/DCOM/ATL] sysfp

[Other] sdh

[Windows Develop] SDH

[VHDL-FPGA-Verilog] SDHAnalysis

[Linux-Unix] Linux_bc

[Other] FaultManag

[VHDL-FPGA-Verilog] rzn725SDH

[VHDL-FPGA-Verilog] sdh1

[VHDL-FPGA-Verilog] SDH

[VHDL-FPGA-Verilog] SDH_module

[VHDL-FPGA-Verilog] code

[VHDL-FPGA-Verilog] VHDL_SDH

[VHDL-FPGA-Verilog] SDH

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