Search - vhdl 128

[Other resource] 128×16ram

Description: VHDL程序设计的RAM存储器，双端口，128×16比特
Platform: | Size: 863 | Author: petri | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的128细分的步进电机驱动程序

Description: 基于FPGA的128细分的步进电机驱动程序
Platform: | Size: 787587 | Author: F599GTB | Hits:

Description: 设计一个线性相位FIR滤波器（31阶）输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]-Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Platform: | Size: 2641920 | Author: 陈金立 | Hits:

[VHDL-FPGA-Verilog] keyborad

Description: 一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms
Platform: | Size: 1024 | Author: 张风 | Hits:

[VHDL-FPGA-Verilog] vcpwmcpldcar

Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Platform: | Size: 959488 | Author: hxf | Hits:

[VHDL-FPGA-Verilog] 128×16ram

Description: VHDL程序设计的RAM存储器，双端口，128×16比特-VHDL programming RAM memory, dual-port, 128 × 16 bits
Platform: | Size: 1024 | Author: petri | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[Special Effects] djpeg

Description: 实现jpeg图像解码功能。代码设计思路：1, Reconstruct the Huffman/RLE stream to a sequence 2, Arrange the sequence to a matrix using the zigzag scanning backwards 3, Multiply the matrix by quantization table 􀂄 4, Perform inverse DCT 5, Shift the values by +128 6, Transform back to RGB color space -Realize jpeg image decoding capabilities. Code design: 1, Reconstruct the Huffman/RLE stream to a sequence2, Arrange the sequence to a matrix using the zigzag scanning backwards3, Multiply the matrix by quantization table
Platform: | Size: 186368 | Author: 颜新卉 | Hits:

[VHDL-FPGA-Verilog] LCD

Description: 通过VHDL写的128*32液晶驱动接口。-Through VHDL to write 128* 32 LCD driver interface.
Platform: | Size: 158720 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] 12864

Description: 用VHDL 语言驱动DM128*64LCD程序-Using VHDL language driver DM128* 64LCD procedures
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] Lcd-12864

Description: 这是一个用ALTER公司FPGA控制外部128×64液晶的程序，很实用，希望大家下载！-This is a company with FPGA control ALTER external 128 × 64 LCD procedures, it is useful, I hope you download!
Platform: | Size: 2652160 | Author: 裴跃生 | Hits:

[VHDL-FPGA-Verilog] wannianli

Description: 采用VHDL语言编写的万年历程序，可在液晶上显示！-Using VHDL language calendar procedures, can be displayed on the LCD!
Platform: | Size: 20480 | Author: dqtyp | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
Platform: | Size: 961536 | Author: Arun | Hits:

[Other] xztu

Description: QAM星座图的原理和应用 16 32 64 128 256QAM星座图-QAM constellation diagram and application of the principle of 16 32 64 128 256QAM constellation diagram
Platform: | Size: 178176 | Author: 黄诗杰 | Hits:

[Crack Hack] aes_cipher_top

Description: 密钥扩展模块的接口如图4.4。clk为系统时钟，kld为输入的加载信号，key为输入的128位密钥数据，wo_0, wo_1, wo_2, wo_3分别为输出的密钥列
Platform: | Size: 3072 | Author: eee | Hits:

[VHDL-FPGA-Verilog] pn127

Description: 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
Platform: | Size: 446464 | Author: lee | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[VHDL-FPGA-Verilog] 12864

Description: 基于VHDL语言，控制液晶12864显示的源程序，非常好用。-Based on the VHDL language, control of liquid crystal display source code 12864, very easy to use.
Platform: | Size: 2476032 | Author: qiuhaimei | Hits:

[VHDL-FPGA-Verilog] FPGA_128_AES_decryption

Description: 以FPGA具體實現的128-bit AES decryption，包括介紹文件以及源碼。-FPGA-based 128-bit AES decryption
Platform: | Size: 17012736 | Author: Vlog | Hits:

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[Other resource] 128×16ram

[VHDL-FPGA-Verilog] 基于FPGA的128细分的步进电机驱动程序

[VHDL-FPGA-Verilog] FIR31

[VHDL-FPGA-Verilog] keyborad

[VHDL-FPGA-Verilog] vcpwmcpldcar

[VHDL-FPGA-Verilog] 128×16ram

[VHDL-FPGA-Verilog] ip_fft128

[Special Effects] djpeg

[VHDL-FPGA-Verilog] LCD

[VHDL-FPGA-Verilog] 12864

[VHDL-FPGA-Verilog] Lcd-12864

[VHDL-FPGA-Verilog] wannianli

[Crack Hack] aes_crypto_core_latest.tar

[Other] xztu

[Crack Hack] aes_cipher_top

[VHDL-FPGA-Verilog] pn127

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] RAM

[VHDL-FPGA-Verilog] 12864

[VHDL-FPGA-Verilog] FPGA_128_AES_decryption

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