Search - vhdl DE2

[VHDL-FPGA-Verilog] DE2_Synthesizer

Description: 利用此源碼可以使用ALTERA DE2開發板將鍵盤變成一部電子琴-Use this source code can use the ALTERA DE2 development board will be turned into an electric piano keyboard
Platform: | Size: 109568 | Author: 林哲 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_Test

Description: DE2彩色LCM的Demo测试程序.包括DE2接口和驱动程序-DE2 color LCM the Demo test procedure. Including driver interface and DE2
Platform: | Size: 696320 | Author: 王海江 | Hits:

[assembly language] DE2_SD_Card_Audio

Description: FPGA开发,DE2开发板上实现,从SD卡读出MP3文件并播放,(即是开发一个简单的MP3播放器)-FPGA development, DE2 development board realize, from the SD card to read out and play MP3 files, (that is, the development of a simple MP3 player)
Platform: | Size: 1291264 | Author: 朱明 | Hits:

[Com Port] uart

Description: 开源的串口通信程序，用vhdl 编写的，已通过测试，在DE2的开发板上能够运行。-Open source serial communication procedures, prepared by using VHDL, has been tested in the DE2 development board to run.
Platform: | Size: 2048 | Author: caijl88 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_Test

Description: DE2控制LCD显示，VHDL编写对LCD的控制，TRDB_LCM显示器 teraslc公司生产-DE2 control LCD display, VHDL prepared for LCD control, TRDB_LCM displays produced teraslc
Platform: | Size: 4096 | Author: 白雪 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_Num

Description: 基於DE2系統的LCM verilog code,在LCM右下方顯示數字,每按一次按鍵數字會加1,顏色也會改變-Based on the DE2 System LCM verilog code, in the lower right corner shows the number of LCM, every time key figures will be one color may also be changed
Platform: | Size: 1092608 | Author: Emuil | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Platform: | Size: 475136 | Author: uuk | Hits:

[SCM] DE2_UserManual

Description: Altera de2 开发板的使用指南，论述了DE2开发板所有配套实例的使用方法-Altera de2 development board
Platform: | Size: 2759680 | Author: 陈建 | Hits:

[VHDL-FPGA-Verilog] DE2_WEB

Description: 用DE2板子实现的音频分析器,需要安装quartus2,硬件需要DE2的板子-DE2 board using the Audio Analyzer realize the need to install quartus2, the hardware needs of the DE2 board
Platform: | Size: 8626176 | Author: 任迎 | Hits:

[VHDL-FPGA-Verilog] mid-filter

Description: 用vhdl语言实现的中值滤波,硬件需要DE2板-VHDL language used to achieve the median filter, the hardware need to DE2 board
Platform: | Size: 1270784 | Author: 任迎 | Hits:

[VHDL-FPGA-Verilog] main

Description: altera de2 sd 卡源程序。调试成功的-altera de2 sd card source. Debugging success
Platform: | Size: 1024 | Author: 娟娟 | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

Description: 用于altera公司DE2开发板上SD_Card_Audio的实例-DE2 development company for the altera board SD_Card_Audio examples
Platform: | Size: 1600512 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] DE2_CCD_CV

Description: altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver
Platform: | Size: 12056576 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] DE2_LCM_CCD

Description: 在altera DE2 的开发板上采集图像，到lcd显示的原程序。-In altera DE2 development board collecting images, lcd display to the original procedure.
Platform: | Size: 3439616 | Author: alison | Hits:

[VHDL-FPGA-Verilog] DE2_with_VGA_LCM

Description: altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
Platform: | Size: 2924544 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: DE2开发板提供的四端口SDRAM驱动，用户不需要对SDRAM直接操作，把SDRAM对用户透明化-DE2 development board provides four-port SDRAM drive, users do not need to direct the operation of the SDRAM, the SDRAM transparent to users
Platform: | Size: 15360 | Author: 旺仔 | Hits:

[VHDL-FPGA-Verilog] DE2_VGA3

Description: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Platform: | Size: 1275904 | Author: Donghua Gu | Hits:

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[VHDL-FPGA-Verilog] DE2_Synthesizer

[VHDL-FPGA-Verilog] DE2_LCM_Test

[assembly language] DE2_SD_Card_Audio

[Com Port] uart

[VHDL-FPGA-Verilog] DE2_LCM_Test

[VHDL-FPGA-Verilog] DE2_LCM_Num

[VHDL-FPGA-Verilog] sin

[SCM] DE2_UserManual

[VHDL-FPGA-Verilog] DE2_WEB

[VHDL-FPGA-Verilog] mid-filter

[VHDL-FPGA-Verilog] main

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

[VHDL-FPGA-Verilog] DE2_CCD_CV

[VHDL-FPGA-Verilog] DE2_LCM_CCD

[VHDL-FPGA-Verilog] DE2_with_VGA_LCM

[VHDL-FPGA-Verilog] Sdram_Control_4Port

[VHDL-FPGA-Verilog] DE2_VGA3

[Picture Viewer] DE2_CCD

[VHDL-FPGA-Verilog] DE2

[VHDL-FPGA-Verilog] DE2LCD_(VHDL)

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