Search - vhdl JPEG

[Graph program] jpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio/video codec
Platform: | Size: 222208 | Author: | Hits:

[Other] fpga-jpeg

Description: vhdl实现的ＪＰＥＧ嘿嘿嘿嘿圆圆嘿嘿另-VHDL achieve JPEG laughter laughter another round laughter
Platform: | Size: 103424 | Author: window | Hits:

[VHDL-FPGA-Verilog] mdct.tar

Description: 这是06年4月刚刚完成的程序，从opencore.org下载而来。用vhdl语言描写，以及matlab仿真，testbench，以及在xinlinx上的综合。 The MDCT core is two dimensional discrete cosine transform implementation designed for use in compression systems like JPEG. Architecture is based on parallel distributed arithmetic with butterfly computation. -This is April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete cosin e transform implementation designed for use in JPEG compression systems like. Architecture i 's based on parallel distributed arithmetic wit h butterfly computation.
Platform: | Size: 1767424 | Author: 陈朋 | Hits:

[VHDL-FPGA-Verilog] jpeg_vhdl_src

Description: JPEG的硬體設計採用的是VHDL設計,有源碼-JPEG hardware design using VHDL design source code
Platform: | Size: 288768 | Author: 黃彥華 | Hits:

[Compress-Decompress algrithms] fft

Description: jpeg压缩中离散余弦变换DCT快速算法代码，使用的是verilog
Platform: | Size: 1024 | Author: 张伟 | Hits:

[Picture Viewer] JPEG_Encode_verilog

Description: Verilog源代码，用来实现JPEG的编码-Verilog source code, used for JPEG encoding
Platform: | Size: 104448 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] fpga-jpeg

Description: jepg verilog example
Platform: | Size: 103424 | Author: 展望 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG标准下图象压缩的VHDL实现工程，包含文档，原代码及测试代码-JPEG image compression standard of VHDL realization of the project, including documentation, source code and test code
Platform: | Size: 1474560 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] fpgajpeg

Description: 基于FPGA的JPEG图像压缩芯片设计 -FPGA-based JPEG image compression chip design
Platform: | Size: 103424 | Author: 倪德 | Hits:

[Special Effects] JPEGDecoder

Description: JPEG解码器的硬件语言描述，主要的描述语言是verilog,用硬件结构实现了解码功能。-JPEG decoder hardware description language, the main language is described in verilog, with hardware structure realize the decoding capabilities.
Platform: | Size: 199680 | Author: liusu | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: 这是一个JPEG的编解码的VHDL程序代码-This is a JPEG codec the VHDL code
Platform: | Size: 1708032 | Author: 叶子 | Hits:

[VHDL-FPGA-Verilog] jpeg

Description: JPEG(Joint Photographic Expert Group,联合摄影专家组)编码的数据执行解压缩的各项功能.JPEG的VHDL实现代码-JPEG (Joint Photographic Expert Group, Joint Photographic Experts Group) encoding of data to implement the various functions of decompression. JPEG realization of VHDL code
Platform: | Size: 3241984 | Author: 陈 | Hits:

[Compress-Decompress algrithms] jpeg

Description: a jpeg compression core
Platform: | Size: 317440 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] jpeg.tar

Description: This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with resolution 352x288). Image resolution is not limited. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image. Its quality is comparable to software solutions.
Platform: | Size: 3416064 | Author: Bill Guan | Hits:

[mpeg mp3] jpeg.tar

Description: jpeg硬件压缩代码，对学习jpeg压缩的同学非常有用-hardware jpeg compression code, the Student Study jpeg compression is very useful
Platform: | Size: 1869824 | Author: ma | Hits:

[Picture Viewer] JPEG

Description: Here is a quite detailed low level design document for the Core: Low Level Design Document for JPEG Encoder
Platform: | Size: 795648 | Author: mahmoud | Hits:

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

Description: JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
Platform: | Size: 796672 | Author: mahmoud | Hits:

[VHDL-FPGA-Verilog] fpga-jpeg

Description: 基于FPGA的JPEG图像压缩，实现JPEG图像的实时压缩-FPGA JPEG compress
Platform: | Size: 103424 | Author: 方映 | Hits:

[VHDL-FPGA-Verilog] JPEG

Description: 本文首先介绍了静态图像压缩（JPEG）编码算法的基本原理、压缩的实现过程及其重要过程的离散余弦变换（DCT）算法的实现原理及软件实现的例程，其次着重介绍了压缩过程中的DCT、量化和编码三个重要步骤的实现原理。-This paper describes the static image compression (JPEG) coding algorithm is the basic principle of compression process of the implementation process and its important discrete cosine transform (DCT) Algorithm theory and software implementation of the routines, followed by highlights of the compression process DCT, quantization and encoding steps in the realization of three important principles.
Platform: | Size: 41984 | Author: xuai | Hits:

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[Graph program] jpeg_src

[mpeg mp3] video_compression_systems

[Other] fpga-jpeg

[VHDL-FPGA-Verilog] mdct.tar

[VHDL-FPGA-Verilog] jpeg_vhdl_src

[Compress-Decompress algrithms] fft

[Picture Viewer] JPEG_Encode_verilog

[VHDL-FPGA-Verilog] fpga-jpeg

[VHDL-FPGA-Verilog] jpeg

[VHDL-FPGA-Verilog] fpgajpeg

[Special Effects] JPEGDecoder

[VHDL-FPGA-Verilog] jpeg

[VHDL-FPGA-Verilog] jpeg

[Compress-Decompress algrithms] jpeg

[VHDL-FPGA-Verilog] jpeg.tar

[mpeg mp3] jpeg.tar

[Picture Viewer] JPEG

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

[VHDL-FPGA-Verilog] fpga-jpeg

[VHDL-FPGA-Verilog] JPEG

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