Search - vhdl SOC

[Other resource] 8051的内核(vhdl)

Description: 最完整最实用的8051的软核，用VHDL语言编写全部原代码，并有详细的注释介绍，对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference
Platform: | Size: 213510 | Author: czy | Hits:

[VHDL-FPGA-Verilog] 8051的内核(vhdl)

Description: 最完整最实用的8051的软核，用VHDL语言编写全部原代码，并有详细的注释介绍，对开发增强型多功能单片机或RSIC单片机内核和单片机SOC应用非常有参考价值-most complete most practical of the 8051 soft-core, with all the preparation VHDL source code, and the Notes for a detailed briefing on the development of an enhanced multi-purpose microcontroller core or RSIC microcontroller and microprocessor applications SOC very valuable reference
Platform: | Size: 212992 | Author: czy | Hits:

[VHDL-FPGA-Verilog] SoC_WishboneSystem

Description: SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 91136 | Author: 周华茂 | Hits:

[ARM-PowerPC-ColdFire-MIPS] or2000

Description: 这是一个MIPS架构的开发的CPU软核OR2000，比OR1200更高的版本，里面还有SOC程序，多次MPW流片成功-This is a MIPS architecture to develop the CPU soft-core OR2000, higher than OR1200 version, there is also SOC procedures, many times MPW silicon success
Platform: | Size: 102400 | Author: liming | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: 同步动态RAM的控制电路VHDL源代码,在SOC开发中可以直接应用-Synchronous Dynamic RAM control circuit VHDL source code, in the SOC development can be applied directly
Platform: | Size: 90112 | Author: 26 | Hits:

[Software Engineering] SOC_CCD

Description: 基于SOC的线阵CCD图像采集单元设计.pdf-SOC based on the linear array CCD image acquisition unit design. Pdf
Platform: | Size: 506880 | Author: 王剑雨 | Hits:

[Other] SoC

Description: SoC设计与测试,很不错的书籍，可以说是经典了．学习ＳＯＣ必读-err
Platform: | Size: 4675584 | Author: 中英文对照 | Hits:

[VHDL-FPGA-Verilog] uart_serial

Description: UART接口的VHDL源代码，成功应用于SOC项目开发中，请勿用于商业用途。-UART interface of the VHDL source code, successfully applied in the development of SOC projects, not for commercial purposes.
Platform: | Size: 12288 | Author: xiaojian | Hits:

[VHDL-FPGA-Verilog] ARM7_verilog

Description: arm 7 verilog code used setup soc
Platform: | Size: 62464 | Author: chen | Hits:

[VHDL-FPGA-Verilog] pic16f84

Description: 用VHDL语言实现的pic16f84，研究SOC嵌入式系统设计很有帮助-Achieved using VHDL language pic16f84, research helpful SOC Embedded System Design
Platform: | Size: 48128 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] DES_IP

Description: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: | Size: 23552 | Author: charity | Hits:

[Program doc] TheResearchAndIPDesignOfSMBusBasedSmartBattery

Description: 本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有良好的性能。-This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.
Platform: | Size: 256000 | Author: caorui | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] FPGA_DESIGNED

Description: 曾经的硕士论文，基于FPGA的8051的soc核研究，用FPGA实现的51核，对FPGA的学习很有帮助-Have master' s thesis, based on the FPGA of the soc of the 8051 nuclear research, with FPGA to achieve the 51 nuclear, helpful for learning FPGA
Platform: | Size: 5193728 | Author: 菠萝 | Hits:

[VHDL-FPGA-Verilog] soc-gr0040-010309

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 406528 | Author: urga turg | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[Other] Soc

Description: 这是片上系统设计（SOC)教材，讲解比较清楚，容易理解，是一本很好的入门教材-This is a system-on-chip design (SOC) materials, to explain more clearly, easy to understand, is a good entry-materials
Platform: | Size: 2177024 | Author: xiaoyi | Hits:

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