Search - vhdl am

[Other resource] vhdl程序集

Description: 本人初学VHDL时编的比较系统的VHDL源程序巨实用 -I am learning more systematic series of practical VHDL source Giant
Platform: | Size: 13829 | Author: 李健 | Hits:

[VHDL-FPGA-Verilog] vhdl程序集

Description: 本人初学VHDL时编的比较系统的VHDL源程序巨实用 -I am learning more systematic series of practical VHDL source Giant
Platform: | Size: 13312 | Author: 李健 | Hits:

[SCM] at24c16

Description: 对初学者非常有用的24C16程序,我就是从这个程序开始的- To the beginner extremely useful 24C16 procedure, I am start from this procedure
Platform: | Size: 1024 | Author: 张裕峰 | Hits:

[VHDL-FPGA-Verilog] VHDL_Yifeng_Ke

Description: 原版VHDL语言教程我也是在网上搜索到的，很经典好东东不敢自己独享！-original VHDL Guide I am also in the online search of the classic good Dongdong dare not stay!
Platform: | Size: 2984960 | Author: 刘凯 | Hits:

[VHDL-FPGA-Verilog] Quartus_vhdl

Description: 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
Platform: | Size: 44032 | Author: 刘刚 | Hits:

[Software Engineering] VHDL_EXPERIENCE_Frily

Description: 本人学习VHDL经验的总结,其中包括了本人从学习VHDL开始到现在遇到过的所有问题及其解决方法以及在其他地方看到过的所有个人觉得经典的经验技巧,拿出来与大家分享-I am learning VHDL experience, including my learning VHDL from the beginning up to now all the problems encountered and their solutions as well as in other places have seen all the individuals feel that the experience of classical techniques, and show to share with you
Platform: | Size: 243712 | Author: 张红静 | Hits:

[MPI] fft

Description: 解决FFT的编程问题，赶紧下啊~~很好的，真的，不过不是我编的，高手那转的！-FFT to solve programming problems, quickly, under ah ~ ~ very good, really, but I am not prepared, and master it turn!
Platform: | Size: 1024 | Author: 王斌 | Hits:

[VHDL-FPGA-Verilog] control_wrr

Description: 用VHDL语言实现的以09449为桥接芯片的PCI接口，很高兴与大家共享。-Using VHDL language in order to achieve the 09,449 for the bridge chip s PCI interface, I am very glad to share with you.
Platform: | Size: 3072 | Author: cws | Hits:

[Embeded-SCM Develop] mydds

Description: Direct Digital Synthesis (DDS),最好用的可步进的数字频率发生器的方法，此代码本人亲自编写，用于当年电子设计大赛。注意其中有个模块用于与单片机通信，可以使用、下载到芯片中，仅供学习使用！-Direct Digital Synthesis (DDS), the best use of the digital frequency generator step method, the code I am personally prepared for electronic design contest that year. Attention which has modules for single-chip communication, you can use to download to the chip, only learning to use!
Platform: | Size: 8192 | Author: cjs | Hits:

[VHDL-FPGA-Verilog] DDS-320-modu

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。-320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Platform: | Size: 1250304 | Author: hangyinli | Hits:

[VHDL-FPGA-Verilog] fir6dlms

Description: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Platform: | Size: 1024 | Author: 李允 | Hits:

[VHDL-FPGA-Verilog] VHDh

Description: vhdl.电子琴程序设计.本人从某个地方下. 请大家注意保密.-vhdl. flower design. I am from somewhere under the. Please everyone pay attention to confidentiality.
Platform: | Size: 10240 | Author: 朔夜 | Hits:

[VHDL-FPGA-Verilog] AM

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[Software Engineering] ZX

Description: 本系统以51单片机及FPGA为控制核心，由正弦信号发生模块、功率放大模块、调幅（AM）、调频（FM）模块、数字键控（ASK，PSK）模块以及测试信号发生模块组成-The system of 51 single-chip and FPGA for the control of the core module by the sinusoidal signal, power amplifier module, AM (AM), frequency modulation (FM) module, digital keying (ASK, PSK) signal modules and test modules
Platform: | Size: 105472 | Author: 123 | Hits:

[assembly language] am

Description: 基于matalab simulink中dspbuider实现am调制，将mdl文件转化为vhdl文件，在quartus2里面进行下载验证-Matalab simulink based on the realization of dspbuider modulation am to mdl file into vhdl file, download it in quartus2 authentication
Platform: | Size: 1769472 | Author: 沈友俊 | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

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[Other resource] vhdl程序集

[VHDL-FPGA-Verilog] vhdl程序集

[SCM] at24c16

[VHDL-FPGA-Verilog] VHDL_Yifeng_Ke

[VHDL-FPGA-Verilog] Quartus_vhdl

[Software Engineering] VHDL_EXPERIENCE_Frily

[MPI] fft

[VHDL-FPGA-Verilog] control_wrr

[Embeded-SCM Develop] mydds

[VHDL-FPGA-Verilog] DDS-320-modu

[VHDL-FPGA-Verilog] fir6dlms

[VHDL-FPGA-Verilog] VHDh

[VHDL-FPGA-Verilog] AM

[Software Engineering] ZX

[assembly language] am

[VHDL-FPGA-Verilog] dds_final

[VHDL-FPGA-Verilog] MC1496

[VHDL-FPGA-Verilog] AM

[VHDL-FPGA-Verilog] AM_DE

[VHDL-FPGA-Verilog] eda

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