Search - vhdl avr

[Other resource] embedded_avr_core

Description: 一个嵌入式微avr的vhdl源代码,.大家可以参考一下 -an embedded micro-avr vhdl the source code. We can take a look
Platform: | Size: 55619 | Author: 大为 | Hits:

[VHDL-FPGA-Verilog] maxshiyan

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[VHDL-FPGA-Verilog] AVR_Core

Description: Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)
Platform: | Size: 74752 | Author: Casper | Hits:

[SCM] PinYin_InputMethod_C51

Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Platform: | Size: 14336 | Author: Jawen | Hits:

[SCM] Elevator

Description: AVR单片机ATmega16 开发环境ICC 电梯控制模型 (原创) 测试成功-ATmega16 development environment AVR Singlechip ICC elevator control model (original) test successful
Platform: | Size: 4096 | Author: 谢明强 | Hits:

[VHDL-FPGA-Verilog] d02

Description: 此程序为脉宽测量电路vhdl代码，能够对输入的脉冲信号用10HZ时钟进行计数，输出计数结果。主模块调用显示、计数、控制三个模块实现主体功能-This procedure for pulse width measurement circuit VHDL code, able to input the pulse signal with 10Hz clock count, the output result of the calculation. Main module calls show that counts, control the main functions of the three modules realize
Platform: | Size: 2048 | Author: jingken | Hits:

[VHDL-FPGA-Verilog] AVR

Description: AVR IP CORE 可以直接用于工程的开发和已经通过编译和仿真-AVR IP CORE can be directly used for project development and has passed the compiler and simulation
Platform: | Size: 67584 | Author: 毋杰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPLD

Description: 项目的研究内容是对硅微谐振式加速度计的数据采集电路开展研究工作。硅微谐振式加速度计敏感结构输出的是两路差分的频率信号，因此硅微谐振式加速度计数据采集电路完成的主要任务是测出两路频率信号的差值。测量要求是：实现10ms内对中心谐振频率为20kHz、标度因数为100Hz/g、量程为±50g、分辨率为1mg的硅微谐振式加速度计输出的频率信号的测量，等效测量误差为±1mg。电路的控制核心为单片机，具有串行接口以便将测量结果传送给PC机从而分析、保存测量结果。按研究内容设计了软硬件。软件采用多周期同步法实现高精度，快速度的频率测量方案，并使用CPLD编程实现，这也是最难的地方。硬件采用现在流行的3.3V供电系统，选用EPM240T100C5N和较为实用的AVR单片机芯片Atmega64L，对应3.3V供电系统，串行接口使用MAX3232。最后完成了PCB板的制作，经反复调试后得到了非常好的效果。采集的数据满足项目研究内容中的要求，当提高有源晶振的频率时，精度有大大提高了，此时已远远满足了项目中高精度，快速度测量的要求。另外，采用MFC编程编写了上位机的数据接收和数据处理专用软件，集数据采集，运算，作图，保存功能于一体。此为CPLD语言部分-err
Platform: | Size: 409600 | Author: tancm | Hits:

[VHDL-FPGA-Verilog] AVR_Core.tar

Description: vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
Platform: | Size: 59392 | Author: blur | Hits:

[ARM-PowerPC-ColdFire-MIPS] vhdl

Description: 利用vhdl描述简单mcu，功能类似AVR AT90S1200的单片机的指令系统存储系统等-VHDL description of the use of simple mcu, features similar to the AVR AT90S1200 MCU instruction set, such as storage systems
Platform: | Size: 33792 | Author: yu | Hits:

[SCM] AVR_Core8F.tar

Description: AVR IP core writen in VHDL. It is beta version, working even with AVR studio
Platform: | Size: 58368 | Author: eldis | Hits:

[Software Engineering] avr_core2

Description: avr core porocesssor vhdl source code
Platform: | Size: 62464 | Author: ARS | Hits:

[Software Engineering] AVR_Core

Description: another avr core porocesssor vhdl source code
Platform: | Size: 71680 | Author: ARS | Hits:

[SCM] AVR_Core

Description: AVR的单片机核，和实际的单片机很像，可以根据自己设计使用-AVR microcontroller core, and the actual microcontroller like, can be designed for use according to their own
Platform: | Size: 69632 | Author: 李小虎 | Hits:

[SCM] VHDLAVRIPcore

Description: 使用VHDL语言写的AVR单片机IP核，可以直接使用，已经经过验证，十分珍贵哦-Written in VHDL language using the AVR microcontroller IP core, can be used directly, has proven very valuable oh
Platform: | Size: 76800 | Author: 赵牧 | Hits:

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[Other resource] embedded_avr_core

[VHDL-FPGA-Verilog] maxshiyan

[VHDL-FPGA-Verilog] AVR_Core

[SCM] PinYin_InputMethod_C51

[SCM] Elevator

[VHDL-FPGA-Verilog] d02

[VHDL-FPGA-Verilog] AVR

[ARM-PowerPC-ColdFire-MIPS] CPLD

[VHDL-FPGA-Verilog] AVR_Core.tar

[ARM-PowerPC-ColdFire-MIPS] vhdl

[SCM] AVR_Core8F.tar

[Software Engineering] avr_core2

[Software Engineering] AVR_Core

[SCM] AVR_Core

[SCM] VHDLAVRIPcore

[VHDL-FPGA-Verilog] AVR

[VHDL-FPGA-Verilog] designwithVHDL

[VHDL-FPGA-Verilog] AVR_Core

[VHDL-FPGA-Verilog] vhdl-for-bluetooth

[VHDL-FPGA-Verilog] AVR-CORE

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