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[Other resource] FPGAprogram3

Description: 波特率发生器的设计，这里是实现上述功能的VHDL源程序，供大家学习和讨论。 -baud rate generator design, here is the realization of the above-mentioned functional VHDL source code for all learning and discussion.
Platform: | Size: 3583 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] FPGAprogram3

Description: 波特率发生器的设计，这里是实现上述功能的VHDL源程序，供大家学习和讨论。 -baud rate generator design, here is the realization of the above-mentioned functional VHDL source code for all learning and discussion.
Platform: | Size: 3072 | Author: 许嘉 | Hits:

[assembly language] vhdl

Description: 波特率发生器，一段基于FPGA的源代码，经测试和调试可以使用，所以上载分享。-Baud rate generator, a FPGA-based source code, after testing and debugging can be used, so upload to share.
Platform: | Size: 3072 | Author: 沈冰 | Hits:

[VHDL-FPGA-Verilog] VHDL_UART

Description: VHDL语言的UART串行接口芯片程序,包括数据接收器、数据发送器和波特率发生器等。-VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on.
Platform: | Size: 3072 | Author: liukun | Hits:

[VHDL-FPGA-Verilog] top

Description: RS232串行通信，采用VHDL编程，由波特率发生器，接收器和发送器构成-RS232 serial communication using VHDL programming, by the baud rate generator, receiver and transmitter constitute
Platform: | Size: 1024 | Author: 幸运 | Hits:

[VHDL-FPGA-Verilog] UART_SUCCESS

Description: 实现FPGA和上位机的串口通信，里面由波特率发生器，移位寄存器，计数器，detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function blocks integrated together.
Platform: | Size: 1855488 | Author: zhn | Hits:

[Com Port] uart_zhiwen

Description: RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
Platform: | Size: 109568 | Author: zhangyi | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL

Description: URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simulation program
Platform: | Size: 32768 | Author: 葛棋棋 | Hits:

[Embeded-SCM Develop] baudgen_latest.tar

Description: 波特率发生器的VHDL源码。适用于uart、spi、IIC-Baud rate generator VHDL source code. Apply to uart, spi, IIC
Platform: | Size: 427008 | Author: pyu | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[Technology Management] LastTwoModules

Description: serial reciver in VHDL , first two models ( baud rate generator and Reciver Control )
Platform: | Size: 1504256 | Author: Daniel R. | Hits:

[VHDL-FPGA-Verilog] usefulUART

Description: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA器件设计与实现UART。 -UART is a widely used serial data communication circuits. This design includes UART transmitter, receiver and baud rate generator. Design and Application of EDA technology, based on FPGA device design and implementation of UART.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] URAT_transmitter_receiver_VHDL

Description: 基于UART的VHDL程序，包括顶层程序、波特率发生器程序、UART发送器程序、UART接收器程序4部分程序。有详细注释，并在每个程序后附上一张仿真波形图，便于理解和验证。-UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four part of the program. Detailed notes, and attached to each program a simulation waveform diagram, easy to understand and verify.
Platform: | Size: 36864 | Author: kuaile | Hits:

[Com Port] FPGA_UART

Description: 本例用VHDL语言在FPGA上实现UART的控制，包括了波特率发生器，接收器，发送器，奇偶校验模块，以及滤波模块和测试模块，能让您更透彻的了解UART的工作原理。-In this case the FPGA using VHDL language to achieve UART' s control, including the baud rate generator, receiver, transmitter, parity modules, and filtering module and test module that allows you a more thorough understanding of the working principle of UART .
Platform: | Size: 5170176 | Author: xinhua | Hits:

[VHDL-FPGA-Verilog] UARTVHDL

Description: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA/CPLD器件设计与实现UART。-UART is a widely used serial data communication circuit. The design includes UART transmitter, receiver and baud rate generator. Application of EDA design technology based on FPGA/CPLD device design and implementation of UART.
Platform: | Size: 241664 | Author: 王志慧 | Hits:

[VHDL-FPGA-Verilog] VHDL-based-design-of-SPI

Description: 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design process. According to both send and receive SPI implements the main part of the basic functions. In addition, the design also implements the baud rate generator, digital display features. DE2 board to achieve a circuit with a simple, short development cycle advantages. Full use of the EDA design advantages. Development Process VHDL hardware description language used to describe the design from the ground, sub-module, to fully enhance the designer' s concept of digital logic design.
Platform: | Size: 51200 | Author: 陈添 | Hits:

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