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[Other] vhdl课件

Description: 这是我们电子电路实验课程的讲义,非常适合刚开始学习vhdl语言的读者,讲解比较清晰易懂-This is our experimental electronic circuit course lectures and are very suitable for the beginning of the study and VHDL language readers on the more lucid
Platform: | Size: 9414656 | Author: 韩飞 | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] [eda]vhdl

Description: 福州大学EDA选修课所有实验课程代码。VHDL语言描述（vhd），以及电路图（gdf）-Fuzhou University EDA optional courses in all experimental code. VHDL description (vhd), and circuit (GdF)
Platform: | Size: 222208 | Author: 林锋杰 | Hits:

[Books] VHDLTEACH

Description: VHDL教程 VHDL与数字电路设计 使用手册-VHDL Guide VHDL and digital circuit design manual
Platform: | Size: 4498432 | Author: 20032211 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] VVHDLcodes

Description: 清华大学出版社 VHDL电路设计 一书所有案例源码，省去您敲代码的麻烦，直接仿真吧。-VHDL circuit design a source book all cases, save you the trouble of knocking code, Simulation direct it.
Platform: | Size: 112640 | Author: 潘世雄 | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[Software Engineering] vhdl

Description: VHDL是Very High Speed Integrated Circuit Hardware Description Language的缩写， 意思是超高速集成电路硬件描述语言。对于复杂的数字系统的设计，它有独特的作用。它的硬件描述能力强，能轻易的描述出硬件的结构和功能。这种语言的应用至少意味着两种重大的改变：电路的设计竟然可以通过文字描述的方式完成；电子电路可以当作文件一样来存储。随着现代技术的发展，这种语言的效益与作用日益明显，每年均能够以超过30％的速度快速成长。 这次毕业设计的内容是在简要介绍了VHDL语言的一些基本语法和概念后，进一步应用VHDL，在MAX+plusII 的环境下设计一个电子钟，最后通过仿真出时序图实现预定功能。电子钟的时间显示用到了七段数码管(或称七段显示器)的电路设计，内部的时间控制输出则用到了各种设计，包括：加法计数器，扫描电路，控制秒、分、时的分频电路，各种数制的转换。 -err
Platform: | Size: 473088 | Author: 造型 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL硬件描述语言与数字逻辑电路设计——学习FPGA/CPLD时可参考-VHDL hardware description language and digital logic circuit design- to learn FPGA/CPLD can reference
Platform: | Size: 18691072 | Author: 陨星 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: _TENNIS 基于FPGA的乒乓球游戏硬件电路的设计与实现，有完整的 代码，并有PDF详细说明如何 VHDL - www_pudn_com.files-_TENNIS Table tennis game based on the FPGA hardware circuit design and realization of a complete code, and a detailed account of how PDF has VHDL- www_pudn_com.files
Platform: | Size: 8192 | Author: 张渊杰 | Hits:

[Embeded-SCM Develop] saa7113

Description: saa7113视频解码芯片外围电路设计原理图，可供大家参考设计-saa7113 video decoder chip peripheral circuit design schematics, reference design for everyone
Platform: | Size: 17408 | Author: 穆垚 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 包含TLC5510 VHDL控制程序,TLC7524接口电路程序和URAT VHDL程序与仿真,都已调试过.-TLC5510 VHDL contains control procedures, TLC7524 interface circuit processes and procedures and URAT VHDL simulation, have been debug.
Platform: | Size: 92160 | Author: gillyamylee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块. -Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
Platform: | Size: 13312 | Author: 侯治强 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: VHDL教程 ppt版 绪论 第一章 VHDL基本结构 第二章 VHDL语言元素 第三章 VHDL的描述风格 第四章 VHDL的主要描述语句 第五章 组合逻辑电路设计 第六章 时序逻辑电路设计-Ppt version of VHDL Tutorial VHDL Introduction Chapter I Chapter II the basic structure of VHDL language element of VHDL in Chapter III Chapter IV describes the style of the main description language VHDL Chapter V combinational logic circuit design of Chapter VI of sequential logic circuit design
Platform: | Size: 1081344 | Author: 陈松 | Hits:

[VHDL-FPGA-Verilog] vhdl-intermediate

Description: VHDL进阶，在VHDL初步的基础上，使读者进一步深入了解VHDL语言现象和语句规划的特点，以及应用VHDL表达与设计电路的方法。-Advanced VHDL in VHDL preliminary basis, so that readers further insight into the phenomenon of VHDL language and expressions of the characteristics of planning, as well as the expression and application of VHDL circuit design approach.
Platform: | Size: 404480 | Author: 李芸 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实用VHDL教程,书中内容包括:了解数字集成电路的结构特点 掌握常用EDA工具的基本使用方法 掌握VHDL的基本语法和主要编程要点 掌握常用数字单元电路的VHDL设计 了解数字集成系统的基本设计方法-VHDL Tutorial practical book include: understanding the structural characteristics of digital integrated circuits commonly used EDA tools to master the basic use of VHDL to master basic grammar and the main programming elements commonly used to master the digital unit of VHDL circuit design of digital integrated system to understand the basic design method
Platform: | Size: 3379200 | Author: ff | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PDF格式的书，VHDL的入门教程，对电路设计刚入门的朋友应该有用-PDF format of the book, VHDL Entry Tutorial on circuit design just getting started should be useful to Friend
Platform: | Size: 263168 | Author: joe | Hits:

[File Format] asic_design

Description: 华为,大规模逻辑设计指导书,规格详细，包括：VHDL编写规范，Verilog编写规范，asic设计方法，同步电路设计规则，vhdl电路设计，代码可重用设计，-Huawei, a large-scale logic design guide books, detailed specifications, including: VHDL specification preparation, Verilog specification preparation, asic design, synchronous circuit design rules, vhdl circuit design, reusable code design,
Platform: | Size: 2041856 | Author: feng jee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设 计，包括偶数分频、非 50％占空比和 50％占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使 用的电路，并在 ModelSim 上进行验证。 -This article describes the use of examples in the FPGA/CPLD prescaler to use VHDL to design, including the even-numbered sub-frequency, non-50 duty cycle and 50 duty cycle of the odd-numbered sub-frequency, semi-integer (N+ 0.5) sub-frequency, fractional-N, as well as scores of sub-band frequency points. All can realize through the Synplify Pro or FPGA manufacturers integrated synthesizer to form a circuit can be used and verified in the ModelSim on.
Platform: | Size: 322560 | Author: 黄鹏曾 | Hits:

[File Format] vhdl

Description: 电梯控制器的模块电路，其中一个很重要的模块，是txt格式的代码-Elevator controller module circuit, which is a very important module is the code txt format
Platform: | Size: 1024 | Author: yang | Hits:
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