Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, the lower frequency clock signal. We know that the hardware circuit design clock signal is the most important one of the signals. Below us Divider VHDL description of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency. This is the most simple-frequency circuit, only one counter will be. Platform: |
Size: 1435 |
Author:卢吉恩 |
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Description: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。
以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes Platform: |
Size: 324949 |
Author:赵海东 |
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Description: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。
以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes Platform: |
Size: 324608 |
Author:赵海东 |
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Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display Platform: |
Size: 3293184 |
Author: |
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Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions Platform: |
Size: 4096 |
Author:naturexu |
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Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O Platform: |
Size: 132096 |
Author:xbl |
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Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization. Platform: |
Size: 1024 |
Author:hsj |
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Description: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output. Platform: |
Size: 4096 |
Author:yufang |
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Description: Describe: This VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes-Describe: This is VHDL digital clock, the use of digital control and FPGA design to achieve a number of counter clock, show hours, minutes ,seconds and alarm. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes Platform: |
Size: 92160 |
Author:eric carmen |
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Description: 基于vhdl语言的源代码，主要用于八位的数字时钟进行操作，会用到进位-Vhdl source code based on the language, mainly for the eight digital clock operation, will use the carry Platform: |
Size: 164864 |
Author:zhang |
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Description: VHDL语言编写的一个六十进制计数器（用于分钟），一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。-A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit output. It is one of my total 9 modules that are used to design a digital clock. Platform: |
Size: 207872 |
Author:chzhsen |
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Description: Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl. Platform: |
Size: 28672 |
Author:hatsjoe |
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Description: VHDL Code for a digital bit clock counter and 7 segment display clock on a altera DE2 board with a cyclone II FPGA Platform: |
Size: 950272 |
Author:Casey |
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Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..) Platform: |
Size: 453632 |
Author:zidting |
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Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on.) Platform: |
Size: 454656 |
Author:zidting |
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