Description: 一篇用VHDL实现快速傅立叶变换的论文,包括原理分析和代码实现,印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat Platform: |
Size: 62464 |
Author: |
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Description: VHDL 的FFT 1024点源码。既有VHDL 的,也有Verlog的。比较好用。占用资源少-VHDL source code of the FFT 1024 points. Both VHDL and there are also some of the Verlog. Comparison of ease of use. Occupy less resources Platform: |
Size: 37888 |
Author:张加良 |
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Description: 用fpga实现dsp 的fft算法 其中有几个文档文件和用vhdl写的1024点的fft代码-FPGA dsp realize using the fft algorithm which has a number of document files and the use of VHDL to write the 1024 point fft code Platform: |
Size: 533504 |
Author:阿斯顿 |
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Description: 16点FFT VHDL源程序,The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data
is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for
each of the real and imaginary component of a datum.-16:00 FFT VHDL source code, The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input datais a vector of 16 complex values represented as 16-bit 2 s complement numbers- 16-bits foreach of the real and imaginary component of a datum. Platform: |
Size: 1824768 |
Author:qiyuan |
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Description: 一篇用VHDL实现快速傅立叶变换的论文,包括原理分析和代码实现,印度圣雄甘地大学M.A.学院提供,同时包含使用手册,做FFT很好的-VHDL with a fast Fourier transform papers, including the principle of analysis and code, India Mahatma Gandhi Institute of the University of MA, at the same time contains the user manual, so good FFT Platform: |
Size: 391168 |
Author:费尔德 |
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Description: verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module! Platform: |
Size: 1024 |
Author:刘庆 |
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Description: 该工程实现了一个64点FFT,verilog编写,采用R4SDF结构,通过Modelsim功能仿真,压缩包里有rtl代码,dc脚本,输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report. Platform: |
Size: 1255424 |
Author:ShuChen |
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Description: 该工程实现了一个64点DIF FFT,verilog编写,采用R2MDC结构,通过Modelsim功能仿真,压缩包里有rtl代码,dc脚本,输出报告。-The project implements a 64-point DIF FFT, verilog compiled by R2MDC structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report. Platform: |
Size: 672768 |
Author:ShuChen |
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Description: vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project Platform: |
Size: 364544 |
Author:tejaswini |
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