Description: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down Platform: |
Size: 11264 |
Author:吴雨彤 |
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Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters. Platform: |
Size: 2048 |
Author:tomsontiger |
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Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data. Platform: |
Size: 36864 |
Author:李修函 |
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Description: In this case is a interleaving algorithm code for deinterleaving the code, using VHDL language. This code provide the method of interleaving of the convolutioned code Platform: |
Size: 6144 |
Author:kimdaeyoung |
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