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[Other resource] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23722 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] vhdl程序例子

Description: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Platform: | Size: 168960 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 静态随机存储器(SRAM)设计VHDL代码，已经生成的了-Static random access memory (SRAM) design of VHDL code, has generated a
Platform: | Size: 345088 | Author: 陆见风 | Hits:

[VHDL-FPGA-Verilog] RTL_Memory_AN

Description:
Platform: | Size: 207872 | Author: lijainqiu | Hits:

[VHDL-FPGA-Verilog] RS_5_3_GF256

Description: 用于NAND FLASH CONTROLLER 中的 ecc 各个模块VHDL代码-NAND FLASH CONTROLLER for ecc modules in VHDL code
Platform: | Size: 197632 | Author: 陈佳宜 | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[Technology Management] dds9851

Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments
Platform: | Size: 466944 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] Chapter10

Description: 第十章的代码。 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
Platform: | Size: 6872064 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] EMCRTL

Description: RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16
Platform: | Size: 5120 | Author: Embedded_techie | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: vhdl code for FIFO memory with controler
Platform: | Size: 730112 | Author: Mihai | Hits:

[VHDL-FPGA-Verilog] Altera-memory

Description: 这个软件是altera 芯片对SPIflash的一个控制程序，里面读写测试已经通过。-spi flash code for VHDL
Platform: | Size: 125952 | Author: 周明 | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-Mc

Description: vhdl code for memory controller
Platform: | Size: 128000 | Author: JP | Hits:

[VHDL-FPGA-Verilog] mon

Description: vhdl code for memory core
Platform: | Size: 1024 | Author: JP | Hits:

[VHDL-FPGA-Verilog] Memory-ROMs-RAMs-and-Register-Files

Description: 有关memory的VHDL编码,已经过调制可用，是VHDL的基本编码。-VHDL code for memory.
Platform: | Size: 34816 | Author: 许舒敏 | Hits:

[Other Embeded program] VHDL-code-of-ROM-Based-Instruction-Memory

Description: code for 16 bit instruction memory
Platform: | Size: 1024 | Author: tarunsharma | Hits:

[VHDL-FPGA-Verilog] calc_16_01_14

Description: A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
Platform: | Size: 589824 | Author: Prasad.M | Hits:

[Education soft system] ReadWrite-RAM-VHDL-source-code

Description: This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus lines are 8 Hence, each location can store 8 bits (i.e. 1 byte each) ADR: in std_logc_vector (9 downto 0) D: inout std_logic_vector (7 downto 0) CS: in std_logic OE: in std_logic WR: in std_logic
Platform: | Size: 1024 | Author: ss | Hits:

[VHDL-FPGA-Verilog] FINAL_CODE_CAM

Description: this is a VHDL code for content address memory
Platform: | Size: 177152 | Author: divya | Hits:
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