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[VHDL-FPGA-Verilog] VHDL实例

Description: 各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format
Platform: | Size: 168960 | Author: 付杰 | Hits:

[VHDL-FPGA-Verilog] 8位大小比较器

Description: 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
Platform: | Size: 1024 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[Other] jx

Description: 相位比较器的VHDL实现程序，现行的相位比较器结构往往十分复杂，难于实现。而在一些对精度要求不是很高的领域，简单灵活的相位比较算法有着广阔的市场。-Phase comparator realize the VHDL program, the existing structure of the phase comparator is often very complex and difficult to realize. In some of the precision of the field is not very high, simple and flexible algorithm for phase comparison with a broad market.
Platform: | Size: 1024 | Author: 刘大为 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] 4bitcomp

Description: I try 4-bit comparator here in VHDL
Platform: | Size: 43008 | Author: Bayu | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
Platform: | Size: 1024 | Author: lijinling | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: VHDL code for 16 byte ROM & n bit comparator & a full adder
Platform: | Size: 1024 | Author: Davood | Hits:

[VHDL-FPGA-Verilog] 33_COMP

Description: vhdl做的实数比较器，比较简单，但是实用-The real number vhdl comparator, is relatively simple, but practical
Platform: | Size: 1024 | Author: 高原 | Hits:

[VHDL-FPGA-Verilog] Coding

Description: 这是用VHDL语言编写的4位比较器，用了三种描述进行编写-This is the VHDL language with the 4-bit comparator, used to prepare three kinds of descriptions
Platform: | Size: 4096 | Author: wilson | Hits:

[VHDL-FPGA-Verilog] FPGA_DDS

Description: 基于Cyclone EP1C6240C8 的AD9854 DDS的接口程序，使用FPGA来控制DDS信号的产生，从而达到高频信号产生的目的。 通过FPGA口线模拟AD9854的控制时序。 提供DDS信号波形变换、DDS频率调整、DDS内部比较器使用等功能。-Cyclone EP1C6240C8 of the AD9854 DDS-based interface program, use the FPGA to control the DDS signal generation, so as to achieve high-frequency signal generation purposes. FPGA I lines through the AD9854 analog control of timing. To provide DDS waveform transformation, DDS frequency adjustment, DDS internal comparator to use functions.
Platform: | Size: 1826816 | Author: icemoon1987 | Hits:

[VHDL-FPGA-Verilog] PROGRAM_COMPARATOR

Description: VHDL COMPARATOR PROGRAM
Platform: | Size: 8192 | Author: THIRUNEELAKANDAN | Hits:

[VHDL-FPGA-Verilog] comparator

Description: vhdl code for comparator
Platform: | Size: 97280 | Author: bobby | Hits:

[VHDL-FPGA-Verilog] comparator-using-vhdl

Description: vhdl code for comparator
Platform: | Size: 1024 | Author: chhavi | Hits:

[VHDL-FPGA-Verilog] comparator

Description: 比较器的VHDL代码，采用行为级描述方法-VHDL for comparator
Platform: | Size: 17408 | Author: xiaoheihei | Hits:

[VHDL-FPGA-Verilog] 4-bit-comparator-with-testbench

Description: Create a VHDL representation for a logical circuit of a 4-bit comparator. This comparator will have equal (=), smaller than (<) and larger than (>) output signals.
Platform: | Size: 10240 | Author: zra syaf | Hits:

[VHDL-FPGA-Verilog] 100-vhdl-examples

Description: 资料中包含了100个VHDL语言开发范例，如：加法器、乘法器、比较器、二路选择器、寄存器、综合单元库、函数、七值逻辑线或分辨函数-The data contains 100 examples of VHDL language development, such as: adder, multiplier, comparator, double-selection, register, comprehensive cell library, function, seven-value logic line, or distinguish function.
Platform: | Size: 642048 | Author: 东方不败 | Hits:

[VHDL-FPGA-Verilog] VHDL代码

Description: 实现简单的电子拔河比赛，即两按键模拟，计数器计数，比较器进行比较，最后通过LED灯进行直观显示(To achieve a simple tug of war competition, that is, two button analog, counter count, comparator comparison, and finally through the LED lamp for visual display)
Platform: | Size: 1024 | Author: 很看好 | Hits:

[VHDL-FPGA-Verilog] Comparator

Description: VHDL Bit Comparator
Platform: | Size: 539648 | Author: sidpokhrel | Hits:

[VHDL-FPGA-Verilog] comparator

Description: a vhdl code for comparator
Platform: | Size: 261120 | Author: maleki | Hits:
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