4bitcomp
........\4bitcomp.prj
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\simulation
........\hdl
........\...\4bitcomp.vhd
........\phy_synthesis
........\simulation
........\..........\modelsim.ini
........\..........\modelsim.log
........\..........\presynth
........\..........\........\a_4_bit_comparator
........\..........\........\..................\arch.dat
........\..........\........\..................\arch.dbs
........\..........\........\..................\arch.psm
........\..........\........\..................\_primary.dat
........\..........\........\..................\_primary.dbs
........\..........\........\stimulus
........\..........\........\........\stimulator.dat
........\..........\........\........\stimulator.dbs
........\..........\........\........\stimulator.psm
........\..........\........\........\_primary.dat
........\..........\........\........\_primary.dbs
........\..........\........\testbench
........\..........\........\.........\tbgeneratedcode.dat
........\..........\........\.........\tbgeneratedcode.dbs
........\..........\........\.........\tbgeneratedcode.psm
........\..........\........\.........\_primary.dat
........\..........\........\.........\_primary.dbs
........\..........\........\_info
........\..........\........\_temp
........\..........\run.do
........\..........\tb.log
........\..........\vsim.wlf
........\smartgen
........\........\smartgen.aws
........\stimulus
........\........\a_4_bit_comparator.dsk
........\........\a_4_bit_comparator.hpj
........\........\BtimErrors.log
........\........\files_to_build.txt
........\........\ModelUnderTest_tbench.btim
........\........\ModelUnderTest_tbench.vhd
........\........\waveperl.log
........\synthesis
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\..\project.lst
........\........\viewdraw.ini
........\........\wir