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[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[VHDL-FPGA-Verilog] USB IPcore（带说明）

Description: USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
Platform: | Size: 408576 | Author: 陈友荣 | Hits:

[Other] free_IP_1

Description: 来自于OpenCores组织的开放IP核，非常专业，大牛编写。-OpenCores organizations from open IP core, very professional, big cattle preparation.
Platform: | Size: 2644992 | Author: wangyunshann | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] USB

Description: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Platform: | Size: 1146880 | Author: 蔡飞 | Hits:

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Other] slaveController

Description: 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
Platform: | Size: 56320 | Author: shaqiu | Hits:

[VHDL-FPGA-Verilog] UART_Xilinx_vhd

Description: USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
Platform: | Size: 8192 | Author: tom | Hits:

[VHDL-FPGA-Verilog] usb_latest.tar

Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: | Size: 196608 | Author: liang | Hits:

[Communication] verilog

Description: source code for USB 2.0 fonction core in verilog
Platform: | Size: 57344 | Author: chaitanya | Hits:

[Embeded-SCM Develop] usb20_ipcore_usb_funct

Description: usb 2.0协议的ip核，可用，里面程序有文档说明-usb 2.0 protocol ip core, can be used, which procedures are documented
Platform: | Size: 208896 | Author: KKK | Hits:

[VHDL-FPGA-Verilog] usb

Description: USB完整代码 包括vhdl和verilog两种-usb ip core
Platform: | Size: 260096 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] FT2232H_USB_Core

Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC. This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode. Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput. For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf" Included: VHDL core, NIOS test application, PC test application
Platform: | Size: 6144 | Author: 李涛 | Hits:

[USB develop] USB-1.1-IP-CORE-VHDL

Description: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Platform: | Size: 425984 | Author: sxhfjgl010 | Hits:

[VHDL-FPGA-Verilog] USB_Verilog_IP

Description: USB IP核VHDL源码(使用VHDL实现的USB IP core)-USB IP core VHDL source
Platform: | Size: 143360 | Author: xsp | Hits:

[VHDL-FPGA-Verilog] fpga_usb_serial_20131205.tar

Description: usb serial core is a vhdl synthesizable code, implementing serial data transfer over usb. Combine with a UTMI-compatible transceiver chip, this core acts as a USB device that transfers a byte stream in both directions over the bus
Platform: | Size: 253952 | Author: Doom Train | Hits:
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