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[Other] CCD_USB

Description: 对通用串行总线#$％ 的技术特点和数据传输机制进行了较详细的分析，并讨论了具有#$％ 接口 的数字摄像系统的实现。该系统具有一定的实用价值及应用前景。-23 of the Universal Serial Bus! $ Of the technical features and data transfer mechanism for a more detailed analysis, and discussed with# $ Interface of the digital camera system. The system has a certain practical value and application prospect.
Platform: | Size: 80896 | Author: 简单 | Hits:

[GPS develop] FPGAdatatransport

Description: 本文设计的FPGA模块需要对GPS、便携打印机和串口数据进行处理，将详细介绍如何设计FPGA和不同外设之间的数据传输。同时，在RTL编码中，编写使综合与布局布线效果更佳的代码。-In this paper, the design of FPGA modules need for GPS, portable printers, and serial data processing, will be details on how to design FPGA and data transfer between peripherals. At the same time, RTL coding, synthesis and preparation to make better placement and routing code.
Platform: | Size: 11264 | Author: zhanyi | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] wb_rtc

Description: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Platform: | Size: 8192 | Author: 姓名 | Hits:

[Crack Hack] micro-UARTsource_V

Description: UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications.
Platform: | Size: 5120 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] vhdl_transfer_of_data_types

Description: VHDL, the transfer of data types
Platform: | Size: 5120 | Author: 张菊兰 | Hits:

[Communication-Mobile] ppmVHDL

Description: 红外数据传输速率为4Mbit/s时的编解码4PPM，用vhdl实现的源代码，-Infrared data transfer rate of 4Mbit/s when the codec 4PPM, using VHDL implementation of the source code,
Platform: | Size: 4096 | Author: qin | Hits:

[USB develop] usb

Description: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Platform: | Size: 6144 | Author: polito | Hits:

[Other] sdram_vhdl_lattice

Description: sdram的控制程序，程序分为控制端口模块、时钟模块、数据传输模块及刷新等模块-sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
Platform: | Size: 369664 | Author: 邢雷 | Hits:

[VHDL-FPGA-Verilog] 232

Description: 实现PS/2接口与RS-232接口的数据传输， 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Platform: | Size: 15360 | Author: 包宰 | Hits:

[Other] get_6675_temp_2

Description: MAXII 240 CPLD和6675 开发的0-1023.75度的温度传感数据采集系统，用seg7 LED显示，精度0.25度。探头是K型测温线，Quartus II 6.0调是通过，在cpld开发板上面试验成功-MAXII 240cpld and 0-1023.75 development of 6675 degrees C temperature sensor data acquisition system, using seg7 LED shows that the accuracy of 0.25 degrees. K-type temperature probe is a line, Quartus II 6.0 transfer is approved, the development board cpld successfully tested above. The MAX6675 performs cold-junction compensation and digitizes the signal from a type-K thermocouple. The data is output in a 12-bit resolution, SPI™-compatible, read-only format. This converter resolves temperatures to 0.25°C, allows readings as high as+1024°C, and exhibits thermocouple accuracy of 8LSBs for temperatures ranging from 0°C to+700°C. controller is cpld
Platform: | Size: 464896 | Author: 谭建平 | Hits:

[Communication] ofdm

Description: OFDM communication for data transfer rate at higher speed
Platform: | Size: 753664 | Author: priya | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] rs422

Description: 程序将通过rs422接口传进来的16bit数据转成串行输出的数据-Program will pass through the rs422 interface 16bit data transfer incoming data into a serial output
Platform: | Size: 2693120 | Author: 徐琪 | Hits:

[VHDL-FPGA-Verilog] 4by4

Description: 4输入，4输出，clos网络所用，有利于连接处理器和处理器，处理器和存储器传输数据。-4 inputs, 4 outputs, clos network use is conducive to connecting the processor and processor, processor and memory to transfer data.
Platform: | Size: 1024 | Author: davidsun | Hits:

[Other] FIFO

Description: fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
Platform: | Size: 6144 | Author: zz | Hits:

[Other Embeded program] cp2102(chinese)

Description: 单芯片 USB 转 UART 数据转换器 - 集成的 USB 收发器无需外部电阻 - 集成的时钟无需外部振荡器 - 集成的 512 字节 EEPROM 用于为供应商代码产品代码序列号功率标牌版本号和产品描述等数据提供存储空间 - 片内上电复位电路 - 片内电压调节器3.3V 输出 USB 功能控制器 -符合USB 规范 2.0 全速 (12 Mbps) -通过SUSPEND 和 RI 引脚支持的USB中止状态-Single-Chip USB to UART Data Transfer 􀁺 Integrated USB transceiver no external resistors required 􀁺 Integrated clock no external crystal required 􀁺 Integrated 1024-Byte EEPROM for vendor ID, product ID, serial number, power descriptor, release number, and product description strings 􀁺 On-chip power-on reset circuit 􀁺 On-chip voltage regulator: 3.3 V output 􀁺 100 pin and software compatible with CP2101 USB Function Controller 􀁺 USB Specification 2.0 compliant full-speed (12 Mbps) 􀁺 USB suspend states supported via SUSPEND pins
Platform: | Size: 173056 | Author: lin | Hits:

[VHDL-FPGA-Verilog] Verilog-pci

Description: PCI的FPGA实现，使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
Platform: | Size: 5510144 | Author: zxc | Hits:

[VHDL-FPGA-Verilog] 68013

Description: 使用68013的测试程序，包含68013固件程序-use of cy7c68013,data transfer from usb to pc.
Platform: | Size: 4718592 | Author: 杨小兽 | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:
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