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[Other resource] ref-sdr-sdram-vhdl DL : 1: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2008-10-13 Size : 758.44kb Publisher : 张涛
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
Update : 2025-02-17 Size : 1007kb Publisher : 包盛花
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl DL : 0: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users.
Update : 2025-02-17 Size : 13kb Publisher : hxwf801
[Other] ref-ddr-sdram-vhdl DL : 0: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Update : 2025-02-17 Size : 427kb Publisher : kevin
[VHDL-FPGA-Verilog] DDR_SDRAM_Controller DL : 0: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Update : 2025-02-17 Size : 662kb Publisher : 钟方
[Documents] SDRAM-VHDL DL : 0: SDRAM控制器的VHDL实现，pdf格式，有需要多的，联系我-SDRAM controller VHDL, pdf format, it needs more, Contact
Update : 2025-02-17 Size : 122kb Publisher :
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Update : 2025-02-17 Size : 735kb Publisher : zhao onely
[Other] ddr_ctrlv DL : 0: ddr ram controller vhdl code
Update : 2025-02-17 Size : 54kb Publisher : heyong
[VHDL-FPGA-Verilog] rtl DL : 0: DDR控制器已通过FPGA 验证大家不要错过哦-DDR controller has passed FPGA to verify that we will not miss Oh
Update : 2025-02-17 Size : 51kb Publisher : kin
[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0 DL : 0: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Update : 2025-02-17 Size : 1.61mb Publisher : li ji wei
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2025-02-17 Size : 1007kb Publisher : wfs
[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode DL : 0: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Update : 2025-02-17 Size : 466kb Publisher : fdasfds
[VHDL-FPGA-Verilog] DDRctroll DL : 0: ddr 的fpga 控制器的实现仿真正确-ddr controller fpga to achieve the correct simulation
Update : 2025-02-17 Size : 3.79mb Publisher : gongranli
[VHDL-FPGA-Verilog] tips_vhdl DL : 0: 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序，供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
Update : 2025-02-17 Size : 6.84mb Publisher : 陈少华
[Disk Tools] ddr_contrl DL : 0: DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL.
Update : 2025-02-17 Size : 4kb Publisher : leos
[SCM] DDR2SDRAM DL : 0: 使用MIG工具生成DDR控制器的技术介绍-Using the MIG tool to generate the DDR Controller Technology
Update : 2025-02-17 Size : 10kb Publisher : 林果
[source in ebook] xapp702 DL : 0: 用Virtex4系列FPGA实现DDR控制器的技术介绍-With Virtex4 series FPGA to achieve DDR Controller Technology
Update : 2025-02-17 Size : 211kb Publisher : 林果
[VHDL-FPGA-Verilog] ddr2_controller DL : 0: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.
Update : 2025-02-17 Size : 51kb Publisher : yanxp
[VHDL-FPGA-Verilog] DDR_prj DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
Update : 2025-02-17 Size : 4.56mb Publisher : zhanghe

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