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Search - vhdl debounce - List
[
VHDL-FPGA-Verilog
]
DEBOUNCE
DL : 0
一个小程序,弹跳消除电路,可消除按健的毛刺干扰-a small procedure, bouncing elimination circuit, according to remove the burr-interference
Date
: 2025-07-11
Size
: 1kb
User
:
相耀
[
VHDL-FPGA-Verilog
]
debounce
DL : 0
基于VHDL的键盘去抖动电路 基于VHDL的键盘去抖动电路-VHDL-based keyboard to jitter circuit VHDL-based keyboard to jitter circuit
Date
: 2025-07-11
Size
: 282kb
User
:
叶金伟
[
OS Develop
]
debounce
DL : 0
键盘防抖程序设计,模块化程序;不得不看的好程序,好家伙。-Reduction keyboard programming, modular procedures had a good look at procedures, Goodfellas.
Date
: 2025-07-11
Size
: 1kb
User
:
吴少
[
MiddleWare
]
debounce
DL : 0
按键消抖程序,用Verilog硬件描述语言编写,实现了按键消抖动作-Buffeting eliminate key procedures, using Verilog hardware description language, the realization of the keys for jitter elimination
Date
: 2025-07-11
Size
: 119kb
User
:
liujiani
[
VHDL-FPGA-Verilog
]
Debouncer_Ver2
DL : 0
super fast debounce button on vhdl, xilinx xc
Date
: 2025-07-11
Size
: 1kb
User
:
Terente
[
VHDL-FPGA-Verilog
]
fpga_debounce_filter
DL : 0
fpga debounce filter code in vhdl
Date
: 2025-07-11
Size
: 39kb
User
:
lyle
[
VHDL-FPGA-Verilog
]
debounce
DL : 0
a key debounce logic using VHDL
Date
: 2025-07-11
Size
: 99kb
User
:
tg
[
VHDL-FPGA-Verilog
]
stable_key
DL : 0
按键消抖电路,包含VHDL编写的程序,以及VerilogHDL编写的程序-Key debounce circuit, including a program written in VHDL, as well as programs written VerilogHDL
Date
: 2025-07-11
Size
: 613kb
User
:
路政西
[
VHDL-FPGA-Verilog
]
pingpang
DL : 0
模拟乒乓球游戏机,输入有按键消抖模块,利用两个七段数码管的其中9段来模拟乒乓球的移动路线,中间的数码管兼做球网。-Table tennis simulation game, enter a key debounce module, using two seven-segment digital tube to simulate the Table Tennis section 9 of the mobile line, cater to the middle of the digital net.
Date
: 2025-07-11
Size
: 293kb
User
:
李凡
[
VHDL-FPGA-Verilog
]
vhdl_key_with_debounce
DL : 0
vhdl语言编写的消抖电路,用于按键消抖。-vhdl languages debounce circuit for key debounce.
Date
: 2025-07-11
Size
: 1kb
User
:
[
VHDL-FPGA-Verilog
]
vhdl
DL : 0
键盘去抖,电子密码锁,键盘输入去抖vhdl语言程序-Keyboard debounce
Date
: 2025-07-11
Size
: 4kb
User
:
范萍伟
[
VHDL-FPGA-Verilog
]
Debounce
DL : 0
VHDL编写。在CPLK开发板上设计的数字钟的去抖动电路。该模块相对独立,是学习去抖动的好资料。该模块跟我其它的8个模块配套构成一个数字钟。-Programmed with VHDL.A debouncing circuit which is part of a digital clock designed on a CPLD development board.The module is independent from others and is useful for learning deboucing methods.It is one of my total 9 modules that are used to design a digital clock.
Date
: 2025-07-11
Size
: 195kb
User
:
chzhsen
[
VHDL-FPGA-Verilog
]
fsmd_debounce_exp
DL : 0
vhdl debounce circuit
Date
: 2025-07-11
Size
: 1kb
User
:
rickdecent
[
VHDL-FPGA-Verilog
]
debounce
DL : 0
Switch debounce unit (written in VHDL).
Date
: 2025-07-11
Size
: 20kb
User
:
[
VHDL-FPGA-Verilog
]
VHDL
DL : 0
It s a simple calculator of addition and multiplication using a simple stack, with multiple test benches. The files test-button and debounce are for the use on a board for the correct functionality of the input buttons.
Date
: 2025-07-11
Size
: 17kb
User
:
mandara
[
VHDL-FPGA-Verilog
]
VHDL-key
DL : 0
VHDL语言程序,具有按键消抖哦,程序比较简单,易明白,欢迎大家下载哦-VHDL language program, with key debounce, the procedure is relatively simple, easy to understand, are welcome to download Oh! ! !
Date
: 2025-07-11
Size
: 373kb
User
:
陈建华
[
Other
]
VHDL-key1
DL : 0
利用VHDL程序按键消抖程序,实用性强,易明白,测试成功啦!-VHDL program button debounce procedures, practical, easy to understand, the test is successful!
Date
: 2025-07-11
Size
: 260kb
User
:
陈建华
[
VHDL-FPGA-Verilog
]
the-elimination-of-key-debounce
DL : 0
当按一次按健时,由于按健有反应时间、有抖动,可能你按一次机器感应到几次,防抖就是让在按键正常反应时间内机器只感应一次按键效果,防止误操作,本文是基于FPGA的按键防抖程序代码,用的是VHDL语言,内容包括原理,实际操作及源码等。-When you press a pressing health, because according to health have reaction time, jitter, you may press machine senses a few times, image stabilization in the key is to let the normal reaction time machine button only once induced effects, to prevent misuse, the paper is key FPGA-based image stabilization program code, using VHDL language, including theory, practice and source code, etc.
Date
: 2025-07-11
Size
: 287kb
User
:
李源码
[
Software Engineering
]
debounce
DL : 0
vhdl code of debounce for fpga . you can open it with xilinx and test it with isim or modelsim, it s a good tutorial for writing your first vhdl code and test bench .
Date
: 2025-07-11
Size
: 871kb
User
:
Milad
[
VHDL-FPGA-Verilog
]
按键去抖电路VHDL描述
DL : 0
在开发板FPGA:Spartan-3E 系列,型号:XC3S500E,封装:FGT320,速度-4,利用Xilinx ISE软件,利用VHDL软件编写按键去抖电路,包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Date
: 2025-07-11
Size
: 29kb
User
:
lixilin
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