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[Other] abcdefghijk

Description: 这是一个数字密码锁的VHDL源代码 花了很多时间才弄来的-This a digital code lock VHDL source code spent a lot of time obtained
Platform: | Size: 2048 | Author: 星星 | Hits:

[VHDL-FPGA-Verilog] lockvhdl

Description: Ve一个简单的数字电子密码锁，密码为4 位。 功能 密码输入：每按下一个键，要求在数码管上显示，并依次左移； 密码清除：清除密码输入，并将输入置为”0000”；密码修改：将当前输入设为新的密码；上锁和开锁.-Ve a simple digital electronic locks, passwords for four. Function password: press a key for each request in the digital tube display, and turn left password clear: clear the password, and enter the home as 0000 password modification: the current input set a new password lock and unlock.
Platform: | Size: 154624 | Author: 刘翔居 | Hits:

[VHDL-FPGA-Verilog] mimasuo

Description: 用VHDL编写的数字密码锁,很实用，喜欢请下载-Prepared using VHDL digital code lock, it is practical, likes to download
Platform: | Size: 2048 | Author: ding | Hits:

[VHDL-FPGA-Verilog] LOCK

Description: 以QuatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。-To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.
Platform: | Size: 187392 | Author: cheng sonja | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于EDA技术的数字密码锁源程序代码,大学实训用的着-EDA-based Digital code lock source code, used by the University Training
Platform: | Size: 7168 | Author: shark | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] ElectronicCodeLock

Description: 设计一个通用电子密码锁，具体功能如下：[1]数码输入 [2]数码清除 [3]密码更改 [4]激活电锁 [5]解除电锁-The design of a universal electronic code lock, the specific features are as follows: [1] digital input [2] Digital Clear [3] Password Change [4] to activate electric lock [5] the lifting of electric locks
Platform: | Size: 1024 | Author: 小夏 | Hits:

[VHDL-FPGA-Verilog] CodeLock

Description: 用于模仿密码锁的工作过程。完成密码锁的核心控制功能。可实现数码输入、清除、退位、设置密码、错误提示、系统报警、解除报警、系统关闭等功能。-Used to imitate the work of the code lock process. Locks achieve the core control functions. Digital input can be achieved, clear, step down, set a password, error message, the system alarm, lift the alarm, turn off the functions of the system.
Platform: | Size: 13312 | Author: 胡婕 | Hits:

[Software Engineering] lock

Description: 基于VHDL电子密码锁设计，数码管显示，比较有用的毕业设计，大家可以参考一下-VHDL-based design of electronic locks, digital display, more useful for the design of the graduation, we can refer to
Platform: | Size: 155648 | Author: 孙晓林 | Hits:

[VHDL-FPGA-Verilog] example19

Description: 基于FPGA的数码锁 基于FPGA的数码锁 -FPGA-based FPGA-based digital lock digital lock digital lock-based FPGA
Platform: | Size: 82944 | Author: zhuxiang | Hits:

[SCM] digitalock

Description: 数字密码锁。能实现8位串行输入，可以改密码，并能实现报警功能。-Digital code lock. To achieve 8-bit serial input, you can change passwords, and to achieve the alarm.
Platform: | Size: 1024 | Author: 王睿朝 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mimasuo_VHDL

Description: 用数字逻辑的vhdl编写密码锁的指导书参考一下-Using digital logic vhdl write lock reference guide book
Platform: | Size: 356352 | Author: liguifang | Hits:

[VHDL-FPGA-Verilog] mms

Description: （1）三位数的电子密码锁，通过输入的数字控制密码锁的开关 （2）开锁期间用户可自行设置密码 （3）输入密码正确开锁 -(1) The three-digit electronic code lock, through the input of the digital control lock switch (2) unlock their own during the user to set a password (3), enter the unlock password is correct
Platform: | Size: 183296 | Author: | Hits:

[VHDL-FPGA-Verilog] lock

Description: 设计一个8位串行数字密码锁控制电路 -Design an 8-bit serial digital code lock control circuit
Platform: | Size: 1024 | Author: 冷与 | Hits:

[VHDL-FPGA-Verilog] VHDL_digital_lock_design

Description: VHDL课程的源代码数字密码锁的设计与实现的实验报告，内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
Platform: | Size: 4096 | Author: CXJ | Hits:

[VHDL-FPGA-Verilog] VHDL(LOCK)

Description: 数字密码锁的设计与实现 一．实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计 二．实验内容 设计一个数字密码锁，对其编译，仿真，下载。 数字密码锁具体要求如下： 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时，开锁成功，显示绿灯，否则开锁失败，显示红灯。 3.具有修改密码功能。修改密码时，先开锁，开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后，显示红灯。 5.密码由拔码开关表示，开锁由按键表示。 6具有一个复位按键。按键后，回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Platform: | Size: 18432 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] digital-lock

Description: vhdl课程设计电子密码锁的完整可执行程序，最终评为优秀-vhdl program designed electronic locks complete executable program, and ultimately as good
Platform: | Size: 2732032 | Author: 苏亮亮 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL设计的相关实验，包括4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现。-VHDL design of experiments, including four reversible counters, four reversible binary code- Gray code converter design, the sequence detector design, the ROM-based sine wave generator design, digital lock design and implementation.
Platform: | Size: 49152 | Author: 张联合 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: VHDL实验 数字密码锁的设计与实现-Design and Implementation of VHDL experimental digital lock
Platform: | Size: 1024 | Author: 天行者 | Hits:

[VHDL-FPGA-Verilog] digital-lock

Description: 数字锁的详细设计流程以及VHDL仿真过程和结果，附有源码-The detailed design process digital lock and VHDL simulation process and results, with source code
Platform: | Size: 24576 | Author: WPQ | Hits:
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