Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: VHDL(LOCK) Download
 Description: VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
File list (Check if you may need any files):
mi.vhd
数字密码锁的设计与实现.docx
    

CodeBus www.codebus.net