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[assembly language] rili

Description: 系统功能 带有约会提醒功能的电子日历，具体功能如下： 1、输入起始日期(年月日)、以天为单位计时，数码管显示年月日。 2、能够区分大小月不同的天数并根据年份判断是否为闰二月。 3、可以输入一个日期并开启提醒功能，到时会有警鸣声提醒直到拨动某一特定开关表示已知。 -System function with a date electronic calendar to remind function, specific functions are as follows: 1, enter the start date (year, month and day) to days as a unit time, digital tube display date. 2, able to distinguish between the size of the number of days in different months and years to determine whether the basis of February for the leap. 3, you can enter a date and open the reminder function, there can be a song to remind the police until a specific DIP switches are known to express.
Platform: | Size: 7168 | Author: 徐民 | Hits:

[Other] switch

Description: 四个拨码开关，拨上去对应的前四个LED灯亮，体现了pld io功能的灵活。请把拨码开关右上方的跳线帽跳上，同时拔掉ADC0804的跳线帽。-Four DIP switches, dial up the corresponding first four LED lights, reflect the function of flexible pld io. Please dial code switch at the top right of the jumper cap jumped, and pulled out the jumper cap ADC0804.
Platform: | Size: 64512 | Author: liupeinan | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[SCM] S3_SW

Description: 这个程序是用来测试拨码开关与按键开关的， 当按下按键开关时，相应的led会点亮， 同理打开拨码开关相应的led也会点亮-This procedure is used to test switch DIP switch and button, when pressing the button switch, the corresponding led will light up, open the same token the corresponding DIP switch led will be lit
Platform: | Size: 188416 | Author: 刘飞 | Hits:

[VHDL-FPGA-Verilog] dds_9760_OK

Description: ＤＤＳ信号源程序，用ＶＨＤＬ编的。里面可用拨码开关选择相应的功能：ＦＭ，ＡＳＫ，ＰＳＫ，ＡＭ（这一点实现的不是很好），但其它的很好。频率可达２５Ｍ-DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequency of up to 25M
Platform: | Size: 5096448 | Author: 李逵 | Hits:

[VHDL-FPGA-Verilog] dip_switch_wrapper

Description: 赛灵思开发板dip开关的VHDL源代码，对于硬件开发参考的材料！-Xilinx development board dip switches, VHDL source code for the hardware development of reference materials!
Platform: | Size: 2048 | Author: dc | Hits:

[VHDL-FPGA-Verilog] Mars-EP1C6-F_code2

Description: 此包为FPGA学习板接口实验程序源代码,共包括13个实验程序,有7段数码管,1602液晶显示,12864液晶显示,I2C总线,串口通信,拨码开关等.-The packet interface to FPGA board experimental procedure to study the source code, a total of 13 experimental procedure, there are 7-segment digital tube, 1602 LCD 12864 LCD, I2C bus, serial communication, DIP switch.
Platform: | Size: 4633600 | Author: sunxh092 | Hits:

[VHDL-FPGA-Verilog] test

Description: 将拨码开关全部拨到on，将会看到数码管从 0-9 A-F逐个显示；按下8个按键中的任何一个，对应的LED灯会亮，按第一个按键时，蜂鸣器会响。-All appropriated for the DIP switch on, will see the digital tube display one by one from the 0-9 AF press 8 keys in any one, the corresponding LED lantern light, according to the first button, the buzzer will ring for .
Platform: | Size: 141312 | Author: panda | Hits:

[VHDL-FPGA-Verilog] pwmtest

Description: 拨码开关控制PWM的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Platform: | Size: 175104 | Author: panda | Hits:

[VHDL-FPGA-Verilog] test

Description: 将拨码开关全部拨到on，将会看到数码管从0-9 A-F逐个显示；按下8个按键中的任何一个，对应的LED灯会亮,按第一个按键时，蜂鸣器会响。-All appropriated for the DIP switch on, will see the digital tube display one by one from the 0-9 AF press 8 keys in any one, the corresponding LED lantern light, according to the first button, the buzzer will ring for .
Platform: | Size: 133120 | Author: panda | Hits:

[VHDL-FPGA-Verilog] PWMtest

Description: PWM 转模拟信号 拨码开关控制 PWM 的占空比为16级，分别对应电压3.3伏16分之一的倍数-DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Platform: | Size: 140288 | Author: panda | Hits:

[VHDL-FPGA-Verilog] senduard_50m

Description: 串口发送: 使用串口发送程序接收二进制码（9600波特率） ，用拨码开关控制发送二进制的高四位，按板上的第二个按钮，LED灯会相应的亮起，PC 会收到相应的数据-Serial port to send: Use the serial port to send a program to receive a binary code (9600 baud), with DIP switch control to send binary high-4, according to board the second button, LED lantern lights accordingly, PC will be closed to the corresponding data
Platform: | Size: 194560 | Author: panda | Hits:

[VHDL-FPGA-Verilog] HW3_P1

Description: Clock Controller There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”. -Clock Controller There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CLK”. Your design should pass a predetermined number of pulses to an output “POUT” and then stop, without producing any shortened pulses or glitches. Your circuit should have an 8 position DIP Switch for setting a number “N” and a free running clock input that has a frequency is of 2.55 Mhz . The “START” signal is an asynchronous input signal which will initiate the generator such that when the start button is pushed exactly N clock pulses would be passed to the output “POUT”.
Platform: | Size: 180224 | Author: chris | Hits:

[VHDL-FPGA-Verilog] VHDL8

Description: 一个VHDL拨码开关以及数码管显示的例程，让你更好的明白VHDL查表法的方便，从而减少逻辑单元的使用。-A VHDL DIP switches and digital LED display routine, so you better understand the convenience of VHDL look-up table, thereby reducing the use of logic cells.
Platform: | Size: 2048 | Author: wyb | Hits:

[VHDL-FPGA-Verilog] VHDLdigital

Description: 7段数码管译码器设计与实现 一．实验目的 1.　掌握7段数码管译码器的设计与实现 2.　掌握模块化的设计方法 二．实验内容 设计一个7段数码管译码器，带数码管的4位可逆计数器 [具体要求] 1. 7段数码管译码器 使用拨码开关SW3, SW2, SW1, SW0作为输入，SW3为高位，SW0为低位。 将输出的结果在HEX1，HEX0显示。当输入为‘0000’~‘1111’显示为00~15， 2. 带数码管的4位可逆计数器 将实验三的结果在数码管上显示。结合上次实验，将4位可逆计数器，数码管显示，分别作为两个子模块，实现在数码管上显示的4位可逆计数器。 -7 digital control design and implementation of the decoder 1. Purpose of the experiment 1. To master digital control decoder 7 Design and Implementation 2. Master modular design 2. Experimental content Design of a 7-segment digital tube decoder, with a digital 4-bit reversible counter tube [Specific requirements] 1.7 Duan digital control decoder Use DIP switch SW3, SW2, SW1, SW0 as input, SW3 is high, SW0 is low. The output of the HEX1, HEX0 display. When the input to 0000 ~ 1111 is displayed as 00 to 15, 2. With digital control of the 4-bit reversible counter The experimental results of the three digital tube display. Combined with the previous experiment, the 4-bit reversible counter, digital display, as the two sub-modules, respectively, to achieve in the digital tube display reversible 4-bit counter.
Platform: | Size: 89088 | Author: 爱好 | Hits:

[VHDL-FPGA-Verilog] FPGA_Interface_Equipment

Description: 跑马灯、串口、矩阵键盘、蜂鸣器、I2C、数码管、拨码开关 vhdl verilog源代码（精华）-Marquees, serial port, matrix keypad, buzzer, I2C, digital control, DIP switch vhdl verilog source code (extract)
Platform: | Size: 1591296 | Author: 李银 | Hits:

[Other] dip

Description: 计时器与出租车计价器源代码，编写语言为VHDL-Timer with the taxi meter source code, written language VHDL
Platform: | Size: 39936 | Author: 金鑫 | Hits:

[VHDL-FPGA-Verilog] caideng

Description: 用VHDL语言设计实现一个彩灯控制（8个发光二极管）电路，仿真并下载验证其功能。彩灯有两种工作模式，可通过拨码开关或按键进行切换。 ? 单点移动模式：一个点在8个发光二极管上来回的亮。 ? 幕布式：从中间两个点，同时向两边依次点亮直至全亮， 然后再向中间点灭，依次往复。 -VHDL Language Design and Implementation with a lantern control (8 LEDs) circuit, simulation and download verify its functionality. Carnival has two operating modes, DIP switch or by switching keys. ? Single Mobile Model: a point in eight bright LEDs on the back and forth. ? curtain-style: from the middle of two points, while both sides were lit up to full brightness and then to the mid-point off, and then click back and forth.
Platform: | Size: 1024 | Author: lws | Hits:

[assembly language] vhdl

Description: 译码器设计 实现3-8译码器的门级和行为级设计；完成3-8译码器的门级和行为级设计的仿真，并下载到开发板进行验证。 用拨挡开关K1，K2，K3作为输入的三位二进制码，输出的8位码分别用LED1~LED8 显示-Achieve 3-8 decoder gate-level and behavioral level design complete the 3-8 decoder gate-level simulation and behavioral level design, and downloaded to the development board for verification. Using DIP switch block K1, K2, K3 of the three binary code as input, output 8 yards respectively show LED1 ~ LED8
Platform: | Size: 265216 | Author: 阮智钦 | Hits:

[Other] vhdl---calculator

Description: 基于vhdl语言编写的简易计算器程序，其中主要功能有加减乘和清除，确定等，可实习现连续运算。输出使用七段数码管输出，输入采用拨码开关的方式输入。若计算结果超过99999，蜂鸣器自动报警。-Vhdl language based on simple calculator program, where the main function, subtraction, multiplication and clear, determined, can now practice continuous operation. Output using seven-segment LED output, input mode using DIP switch inputs. If the calculation results of more than 99,999, the buzzer alarm.
Platform: | Size: 1817600 | Author: 张圆 | Hits:
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