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[VHDL-FPGA-Verilog] vhdl

Description: RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
Platform: | Size: 4096 | Author: 波波 | Hits:

[VHDL-FPGA-Verilog] odd_divider_VHDL

Description: 常用1、3、5及任意奇数分频器的VHDL代码实现（原创）-used 1,3,5 and arbitrary odd Divider VHDL code to achieve (original)
Platform: | Size: 1024 | Author: 汤维 | Hits:

[source in ebook] divider

Description: 一个用VHDL语言编写的除法器程序，对从事硬件开发的同志有帮助的。-A language using VHDL divider procedures comrades engaged in hardware development have help.
Platform: | Size: 2048 | Author: maomao | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: vhdl语言描述分频器，实现2、4、8、16……分频，经过实践-description language VHDL divider, 2,4,8,16 ... ... realize frequency, through the practice of
Platform: | Size: 35840 | Author: digua | Hits:

[Software Engineering] 353fpga

Description: 用vhdl实现的除法器-Achieved using VHDL divider
Platform: | Size: 1024 | Author: wenhao sun | Hits:

[VHDL-FPGA-Verilog] divider

Description: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 经过精心设计的除法器的代码，并在FPGA硬件平台实现和验证过的-Meticulously designed divider code, and FPGA hardware platform and tested
Platform: | Size: 1024 | Author: hewg | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[assembly language] VHDLsiweichufaqi

Description: 这是一个利用MAX PULL 制作的VHDL的四位除法器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL produced using VHDL divider of the four procedures, if necessary simulation diagram contact me please call station
Platform: | Size: 2048 | Author: 郭明磊 | Hits:

[VHDL-FPGA-Verilog] what

Description: 除法器,可以很好的实现VHDL除法器的功能对于初学者有很大帮助. -Divider can be very good VHDL divider realize the function of great help for beginners.
Platform: | Size: 1024 | Author: panjun | Hits:

[MPI] vhd_divider

Description: lattice isplever7竟然没有除法库,只好在网上找了老外写的vhdl除法器-lattice isplever7 Treasury did not divide, so the Internet to find a foreigner to write the VHDL divider
Platform: | Size: 6144 | Author: guyh | Hits:

[VHDL-FPGA-Verilog] div

Description: 除法器实验 verilog CPLD EPM1270 源代码-Experimental divider verilog CPLDEPM1270 source code
Platform: | Size: 117760 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Verilog] divider

Description: 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value of N is set up the corresponding figure
Platform: | Size: 1024 | Author: Tomy Lee | Hits:

[VHDL-FPGA-Verilog] divider

Description: 移位快速除法器，通过一次移4位试商实现快速除法功能，较普通减除法器有及其巨大的效率提升-Divider rapid shift by a shift to four test functions of rapid division, as compared with ordinary objects have less efficiency and its huge
Platform: | Size: 1024 | Author: jh | Hits:

[VHDL-FPGA-Verilog] vhdl-devider

Description: 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
Platform: | Size: 1024 | Author: tony | Hits:

[VHDL-FPGA-Verilog] Divider

Description: 一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
Platform: | Size: 148480 | Author: maxpayne | Hits:

[VHDL-FPGA-Verilog] divider

Description: 8位的除法器。用VHDL语言进行设计实现。-8-bit divider. With VHDL design languages.
Platform: | Size: 5120 | Author: 张怡萍 | Hits:

[VHDL-FPGA-Verilog] HG_chufaqi_clajiafaqi

Description: VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
Platform: | Size: 2048 | Author: Huanggeng | Hits:

[VHDL-FPGA-Verilog] The-use-of-VHDL-divider-design

Description: 分频器的各种设计方法， 及源代码，源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。-The use of VHDL divider design
Platform: | Size: 5120 | Author: 王子冉 | Hits:

[VHDL-FPGA-Verilog] VHDL-divider-design

Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
Platform: | Size: 320512 | Author: 黄玲 | Hits:
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