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[VHDL-FPGA-Verilog] dvf

Description: 数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件-CNC dividing frequency of a project- including VHDL source code and compile the relevant documents after
Platform: | Size: 168960 | Author: 吴晨光 | Hits:

[VHDL-FPGA-Verilog] Vhdl1

Description: Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")-Top Level VHDL Code -- simulate the relatively slow progress of an elevator car by dividing the -- clock down by an outrageously high number and scanning the car registers for -- an elevator s next -- (normally the signals used below would be IO pins on the chip, but we have -- no physical elevator, so this is a kind of "diagnostic mode")
Platform: | Size: 3072 | Author: Victor | Hits:

[VHDL-FPGA-Verilog] cnt1_fenpin

Description: 基于vhdl的任意分频程序，可调占空比，-Based on an arbitrary dividing vhdl procedures, adjustable duty cycle,
Platform: | Size: 4096 | Author: 刘诗男 | Hits:

[VHDL-FPGA-Verilog] music_player

Description: 音乐播放器，各模块使用VHDL写的，拥有暂停功能。jishu模块根据时钟信号产生八位递增的地址信号，传到music模块。music模块存放音乐的数据，根据得到的地址输出音阶。tonetab接收到音阶信号后会输出当前的音阶是多少，是否为高八度，用于数码管显示，同时将此音阶需要的分频率传给speaker模块。speaker模块根据接受到的分频比对2M的时钟进行分频，然后送给蜂鸣器发出声音。-Music player, each module written in VHDL, with pause function. jishu module generates eight incremented address signal according to the clock signal, transmitted music module. music module storing music data, based on the obtained address output scale. will scale the output signal is received after tonetab current scale is how much is a high octave, for digital display, while the frequency of this scale needs to pass the sub speaker module. speaker module in accordance with the received frequency-dividing the frequency dividing ratio of the clock 2M, and then sent to the buzzer sound.
Platform: | Size: 1419264 | Author: 马梁 | Hits:

[VHDL-FPGA-Verilog] count

Description: 本实验利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发 时钟，计数器进行加计数，并利用数码管进行显示，当计数到9999 时，从0 开始重新计数。 SW0 为复位开关。当开关拨至高点平时，计数器归0，当开关拨至低电平时，计数器开始计数。 该电路包括分频电路，计数器电路，二进制转BCD 码电路和数码管显示电路。-This experiment uses VHDL hardware description language to design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger Clock, the counter counts up, and the use of digital tube display, when the count to 9999, 0 to re-count. SW0 is the reset switch. When the switch to the high point of ping, the counter to 0, when the switch to low, the counter began to count. The circuit includes a frequency dividing circuit, a counter circuit, a binary-to-BCD code circuit and a digital tube display circuit.
Platform: | Size: 475136 | Author: panda | Hits:

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