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Description: 四位除法器的VHDL源程序-four division of VHDL source
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Size: 1024 |
Author: 张庆辉 |
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Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。
设计平台：MaxPlusII
压缩文件内有详细设计报告
-by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
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Size: 50176 |
Author: johnmad |
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Description: VHDL 8位无符号除法器 试验报告
计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。
其实现方法是，将除法器分为两个状态：等待状态与运算状态。
开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。
-VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
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Size: 82944 |
Author: aa |
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Description: vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design
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Size: 244736 |
Author: 刘建 |
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Description: 这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference.
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Size: 151552 |
Author: 李乐雅 |
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Description: 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
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Size: 741376 |
Author: lele |
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Description: eda7人表决器，设计一个七人表决电路，当参与表决的7人中有4人或4人以上赞同时，表决器输出“1”
表示通过，否则输出“0”表示不通过。
实验时，可用7个电平开关作为表决器的7个输入变量，输入“1”表示表决者“赞同”
输入“0”表示表决者“不赞同”。
-eda7 votes, design a seven-vote circuit, When a vote of seven people who have four or more than four people agree, the division's output "1" indicated, Otherwise output "0" means not through. Experiment, in which seven Level Switches as a vote of seven input variables. the importation of "1", said the vote "endorsed" imported "0" vote, said "do not agree."
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Size: 10240 |
Author: 王哥 |
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Description: 数字系统设计这是有关的相关源代码，有简易CPU 除法器、计数器等 ...[fpdiv_vhdl.rar] - 四位除法器的vhdl源程序 [vhdl范例.rar] - 最高优先级编码器8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使 BR> ...
-Digital System Design This is the underlying source code, a simple CPU divider. Counter etc. ... [fpdiv_vhdl.rar]- 4 division of vhdl source [vh dl example. rar]- highest priority encoder compared to eight for phase three of the vote (the three different description ) Adder Description eight bus transceiver : 74245 (Note 2) address decoder (for m68008) Multiple choice (so that BR
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Size: 1024 |
Author: 张瑞 |
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Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
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Size: 6144 |
Author: 陈丰 |
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Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
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Size: 1024 |
Author: lyy |
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Description: 很实用的一个分频带码，包括奇分频，偶分频，占空比为50％的奇分频,实际工程中很实用-Very useful to a sub-band code, including the odd sub-frequency, dual frequency, duty cycle 50 of the odd sub-frequency, the actual works in very practical
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Size: 290816 |
Author: ecomputer |
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Description: ALU可以实现16种操作（包括加减乘除移位运算等）-ALU can be 16 kinds of operations (including addition and subtraction multiplication and division shift operator, etc.)
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Size: 838656 |
Author: 草野彰 |
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Description: 一个简单的除法器,可以供各位参考!-A simple division, you can for your reference!
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Size: 1024 |
Author: YjLiu |
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Description: 4位alu，包括加减乘除等运算功能，是可综合风格的，包括测试文件-4 alu, including computing functionality, such as addition and subtraction multiplication and division, is a comprehensive style, including the test file
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Size: 2048 |
Author: polozhang |
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Description: 正交频分复用的硬件描述语言实现，atera环境-Orthogonal frequency division multiplexing realize the hardware description language, atera environment
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Size: 2108416 |
Author: 王强强 |
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Description: 电子测量技术
ELECTR0NIC MEASI瓜EMENT TECHN0L0GY
第29卷第3期
2006年6月
PS／2设备接口IP核设计
王 豪黄启俊常 胜
(武汉大学物理学院微电子与固体电子学实验室武汉430072)
摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的
设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
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Size: 126976 |
Author: Morgan |
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Description: 数字系统设计基础教程
本书将数字系统作为一个整体的系统，并按层次结构对数字系统进行划分和论述。论题涉及了数字系统技术的各个方面，如：数制、编码、布尔代数、逻辑门、组合逻辑设计、时序电路、VHDL基本概念、VLSI设计基本概念、CMOS逻辑电路和硅芯片、存储器部件、计算机原理和计算机体系结构基础知识等等。本书将传统的数字电路知识和现代技术相结合，适于大专院校相关专业的学生作教科书之用。 -Digital System Design Essentials book digital system as a whole system, together with a hierarchical structure of digital systems division and expositions. Topics related to digital systems in all aspects of technology, such as: the number system, coding, Boolean algebra, logic gates, combinational logic design, sequential circuits, VHDL basic concepts, VLSI design of the basic concepts, CMOS logic circuits and silicon chips, memory components, computer principles and basic knowledge of computer architecture and so on. This book will be a traditional digital circuit knowledge and modern technology, suitable for students of the relevant professional institutions for use in textbooks.
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Size: 18207744 |
Author: 陨星 |
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Description: 该pdf 详细介绍了 提高除法电路的方法。和设计出发电路时要注意的问题，
介绍了各种除法设计代码-Pdf details the divider circuit to improve the method. And design of the starting circuit should pay attention to the issue of when to introduce a variety of design code division
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Size: 258048 |
Author: gjp_rain |
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Description: 计算器，可实现加减乘除运算并包含数码显示与输入部分。-Calculators, multiplication and division addition and subtraction operations can be realized and includes digital display and input section.
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Size: 9216 |
Author: 寄尘 |
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Description: 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
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Size: 1018880 |
Author: 倪萍波 |
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