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[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Embeded-SCM Develop] 通用存储器包括各种类型存储器的VHDL描述

Description: 通用存储器包括各种类型存储器的VHDL描述， 如FIFO，双口RAM等VHDL代码库
Platform: | Size: 617824 | Author: hanker3 | Hits:

[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[VHDL-FPGA-Verilog] ramlib_06

Description: 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。-This is a FIFO of the VHDL program. . . Please download the U.S. share.
Platform: | Size: 577536 | Author: 张亚伟 | Hits:

[VHDL-FPGA-Verilog] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家-VHDL the ram and fifo model code contains a large number of manufacturers
Platform: | Size: 1678336 | Author: SL | Hits:

[OS Develop] FIFO

Description: fifo.v verilog实现的先进先出存储器-fifo.vverilog realize the FIFO memory
Platform: | Size: 2048 | Author: patrick | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[SCM] FIFO

Description: FIFO中文应用笔记，对学习单片机RAM、大量数据处理很有帮助。-FIFO notes
Platform: | Size: 1136640 | Author: chenlei | Hits:

[Embeded-SCM Develop] VHDL

Description: 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
Platform: | Size: 22528 | Author: xugx | Hits:

[VHDL-FPGA-Verilog] connect20090223

Description: fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
Platform: | Size: 468992 | Author: 张菁 | Hits:

[VHDL-FPGA-Verilog] ram

Description: a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
Platform: | Size: 1024 | Author: sri | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[OS Develop] program

Description: 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Platform: | Size: 3072 | Author: shao | Hits:

[Other] FIFORAM

Description: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Platform: | Size: 331776 | Author: SMILE | Hits:

[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta

Description: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Platform: | Size: 16619520 | Author: Aleks | Hits:
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