Description: Direct Digital Synthesis (DDS),最好用的可步进的数字频率发生器的方法，此代码本人亲自编写，用于当年电子设计大赛。注意其中有个模块用于与单片机通信，可以使用、下载到芯片中，仅供学习使用！-Direct Digital Synthesis (DDS), the best use of the digital frequency generator step method, the code I am personally prepared for electronic design contest that year. Attention which has modules for single-chip communication, you can use to download to the chip, only learning to use! Platform: |
Size: 8192 |
Author:cjs |
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Description: 基于FPGA的DDS信号发生器的简单实现。DDS（直接数字合成）是近年来迅速发展起来的一种新的频率合成方法。这种方法简单可靠、控制方便，且具有很高的频率分辨率和转换速度，非常适合快速跳频通信的要求。 -FPGA-based signal generator DDS simple to achieve. DDS (direct digital synthesis) is a rapidly in recent years developed a new method of frequency synthesis. This method is simple and reliable, convenient control, and has a very high frequency resolution and conversion speed, very suitable for fast frequency-hopping communication requirements. Platform: |
Size: 9216 |
Author:洪利平 |
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Description: 模拟数字通信通道，将离散数据利用奇偶效验码编码，FSK调制后，发送，接收端解调解码后还原-Analog-to-digital communication channel, the use of discrete data to be well-tested code parity coding, FSK modulation, the transmission, the receiving end to restore the decoded demodulation Platform: |
Size: 252928 |
Author:Andy Hu |
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Description: The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented.
The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940).
The design is fully pipelined for maximum throughput. Platform: |
Size: 1239040 |
Author:Arun |
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Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission is an important digital communication system components. In digital communications, some occasions may, after modulation and demodulation process, and on the base-band signals transmitted directly. AMI code using the turn signal inversion, there may be zero Silian phenomenon, which is not conducive to the receiving end of the timing signal extraction. HDB3 code and its non-DC components, and even less low-frequency components of 0 up to more than three the number of characteristics such as timing signals for the recovery of very favorable, and the Association has become the CCITT recommended base-band transmission-type, one code. In this paper, the use of VHDL language in the data transmission system HDB3 encoder has been designed. Platform: |
Size: 108544 |
Author:shashou |
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Description: 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第四部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the fourth part of the digital communication system for modeling and design of friends interested in learning reference. Platform: |
Size: 1661952 |
Author:wangjianan |
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Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments Platform: |
Size: 466944 |
Author:xiang |
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Description: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output. Platform: |
Size: 4096 |
Author:yufang |
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Description: 这本规范的一部分，承担了开发的一种编码方法的需求不断增长，可
便利的天然和合成的活动图像和相关的自然人或可视对象
合成的声音，如数字存储媒体，各种应用互联网，有线或各种形式的
无线通讯等本规范的使用意味着运动视频可以被操纵的
一种电脑数据形式，可以在不同的存储介质传播，并收到超过储存
现有和未来的网络，对现有和未来的广播频道的分发。-This part of this specification was developed in response to the growing need for a coding method that can
facilitate access to visual objects in natural and synthetic moving pictures and associated natural or
synthetic sound for various applications such as digital storage media, internet, various forms of wired or
wireless communication etc. The use of this specification means that motion video can be manipulated as
a form of computer data and can be stored on various storage media, transmitted and received over
existing and future networks and distributed on existing and future broadcast channels. Platform: |
Size: 1475584 |
Author:xuai |
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Description: 通信系统数字信号调制，振幅监控ask信号的调制和解调的VHDL代码-Communication systems digital signal modulation, amplitude control ask signal modulation and demodulation of the VHDL code for Platform: |
Size: 1024 |
Author:lihao |
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Description: 数字通信系统振幅键控ASK信号和频移键控FSK的调制与解调的VHDL代码-ASK amplitude shift keying digital communication system signal and the frequency shift keying modulation and demodulation of the VHDL code for Platform: |
Size: 2048 |
Author:lihao |
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Description: 数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码-Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for Platform: |
Size: 1024 |
Author:lihao |
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Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。
基于达到达到达到的信号发生器的源程序-Digital baseband signal transmission is a digital communications system, an important component. In digital communication, there are some occasions, may from time through the carrier modulation and demodulation process, the base-band signal for direct transmission. AMI code signal using alternating inversion, there may be four to zero with the phenomenon, which is not conducive to the receiving end of the timing signal extraction. The HDB3 code because of its non-DC components, low-frequency components, and even a small number of 0 up to more than three characteristics, while the timing signal recovery is very favorable, and has become CCITT Association recommended one of baseband transmission pattern. In this paper the use of VHDL language for data transmission system in the HDB3 encoder has been designed. Based on the signal generator to achieve to reach to reach the source Platform: |
Size: 3072 |
Author:成风 |
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Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar Platform: |
Size: 223232 |
Author:平凡 |
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Description: 用于无线通信中的数字下变频，主要关注NCO设计还有使用cordic算法实现坐标变换和解调！-For wireless communication of digital down conversion, the main concern there NCO design algorithm using cordic coordinate transformation and demodulation! Platform: |
Size: 2469888 |
Author:peter |
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Description: 基于FPGA的BPSK数字调制器的实现，对于学习通信专业的人应该有些帮助-FPGA-Based Digital Modulator BPSK, for people to learn communication professional should be some help Platform: |
Size: 432128 |
Author:李博 |
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Description: all digital fm receiver using vhdl
programming language project for electronics and communication engineering students. Platform: |
Size: 1545216 |
Author:Rahul |
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Description: 本书为VHDL教材，偏重于应用，主要内容包括图像与高速处理、嵌入式处理器、串行通信、数字滤波器、存储器、PS/2鼠标接口、PS/2键盘接口、VGA显示接口-Book VHDL textbook emphasis on the application, the main content including images and high-speed processing, embedded processors, serial communication, digital filters, memory, PS/2 mouse interface, PS/2 keyboard interface, VGA display interface Platform: |
Size: 11414528 |
Author:James |
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Description: 数字通信同步技术的MATLAB与FPGA实现一书的VHDL代码-The VHDL code for the book of digital communication techniques with MATLAB and FPGA realization Platform: |
Size: 14424064 |
Author:queen |
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Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。
要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示；
数据格式为1位起始位、8位数据位和一位停止位；
上位计算机发送接收软件可使用“串口调试器“软件；
发送和接收数据时，由两个LED分别指示。
发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button.
Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively;
The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit;
The upper computer sends and receives the software, and the serial debugger can be used;
When sending and receiving data, instructions are given by two LED respectively.
Play: Auto postback function, receive special characters (custom), change baud rate automatically.) Platform: |
Size: 2948096 |
Author:淡淡的意识
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