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[Other resource] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23722 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] vhdl程序例子

Description: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Platform: | Size: 168960 | Author: 王力 | Hits:

[OS Develop] ARM_00_OS

Description: 看看ARM菜鸟在ARM7上写的操作系统——ARM圈圈操作系统 最近在ADuC7027上写了一个ARM_00_OS，头都写晕了，发上来给大家一起来看看。 任务按优先级调度，如果处于就绪态且优先级最高的任务有两个或更多，则按时间片轮循调度。 支持任务创建、任务删除、内存分配、简单的消息、简单的设备管理、CPU及内存等使用统计等功能。 任务可处于ARM模式或THUMB模式，在创建任务时，要指定任务所处于的模式。 从这里下载整个文件包：http://blog.21ic.com/more.asp?name=computer00&id=16341 -look at birdie in ARM ARM7 written in the operating system-- the operating system ARM circle recently in ADu C7027 write a ARM_00_OS, write head dizzy, deputy undersecretary for everyone to see. Tasks according to priority scheduling, in place if the state but the highest priority tasks of two or more, according to the time-Round Robin scheduling. Support mission to create, delete tasks, memory allocation, the simple information, a simple device management, CPU and memory usage statistics capabilities. At tasks THUMB ARM model or models in the creation mandate, the mandate should be designated at a model. From here to download the whole package : http :// blog.21ic.com/more.asp name = computer00
Platform: | Size: 360448 | Author: Computer00 | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] 6FloorLift

Description: 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关，电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式（上升或者下降）指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层，经过1秒电梯门打开，开门4秒后，电梯门关闭（开门指示灯灭），电梯继续运行，直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号，并按照电梯运行规则按顺序响应，每个请求信号保留至有电梯响应后消除。 6、初始状态为一层开门，第一层不用向下开关，最高层不用向上开关。 7、电梯运行规则：当电梯上升时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到下楼请求的最高楼层，然后进入下降模式。当电梯处于下降模式时与上升正好相反。 -design of a six-story elevator controller. Elevator Controller in accordance with the requirements of passengers automatically, the device. 1, installed on each floor elevator entrance next request switches, elevator begins to reach the level of customer stops request switch. 2, the location of elevator and escalator installations instructions operation mode (up or down) device instructions. 3, Elevator per second floor landing. 4, the lift reached a request stops floors seconds after an elevator doors open door four seconds later, elevator doors closed (to open the door to eliminate light), the continued operation of the lift, End until the implementation of the final request for a signal to stay in the current layer. 5, the lift will lift internal and external memory signal to all reques
Platform: | Size: 2048 | Author: zheng | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 静态随机存储器(SRAM)设计VHDL代码，已经生成的了-Static random access memory (SRAM) design of VHDL code, has generated a
Platform: | Size: 345088 | Author: 陆见风 | Hits:

[VHDL-FPGA-Verilog] RTL_Memory_AN

Description:
Platform: | Size: 207872 | Author: lijainqiu | Hits:

[VHDL-FPGA-Verilog] verilog_risc

Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。 RISC状态机经优化可实现高效的流水线操作。 RISC 中的数据线为16位。 在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前 对这16个数进行排序，从大到小放置在18到33的位置 求出前16个数的平均数，放在34的位置 基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。 因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion.
Platform: | Size: 129024 | Author: lyn | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[Other] A_First_Couse_in_Digital_Systems_Design_An_Integra

Description: 数字系统设计基础教程 本书将数字系统作为一个整体的系统，并按层次结构对数字系统进行划分和论述。论题涉及了数字系统技术的各个方面，如：数制、编码、布尔代数、逻辑门、组合逻辑设计、时序电路、VHDL基本概念、VLSI设计基本概念、CMOS逻辑电路和硅芯片、存储器部件、计算机原理和计算机体系结构基础知识等等。本书将传统的数字电路知识和现代技术相结合，适于大专院校相关专业的学生作教科书之用。 -Digital System Design Essentials book digital system as a whole system, together with a hierarchical structure of digital systems division and expositions. Topics related to digital systems in all aspects of technology, such as: the number system, coding, Boolean algebra, logic gates, combinational logic design, sequential circuits, VHDL basic concepts, VLSI design of the basic concepts, CMOS logic circuits and silicon chips, memory components, computer principles and basic knowledge of computer architecture and so on. This book will be a traditional digital circuit knowledge and modern technology, suitable for students of the relevant professional institutions for use in textbooks.
Platform: | Size: 18207744 | Author: 陨星 | Hits:

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

Description: 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three experiments _SOPC_LED programmer _Flash the basis of four experiments of five experiments _ timer six experimental basis _ keys, as well as experimental experimental PIO interrupt I _ 7 card use, these laboratories used the SOPC BUILDER with NOIS ii, the use of Verilog to prepare, there are no experimental test panels and plates can be used to learn. The second also includes: FPGA development board of the links between memory, multi-processor documents, USB_UART such as documents, useful documents, you will not regret it a sure!
Platform: | Size: 6065152 | Author: yuezhiying_007 | Hits:

[VHDL-FPGA-Verilog] vga_hex_disp

Description: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Platform: | Size: 18432 | Author: submars | Hits:

[VHDL-FPGA-Verilog] memory_example

Description: This simple example allows you to get familiar with Active-HDL s Memory Viewer.
Platform: | Size: 10240 | Author: leiyu | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[OS program] jtag

Description: JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on). JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info. -JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter. This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on). JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info.
Platform: | Size: 957440 | Author: asdf | Hits:

[VHDL-FPGA-Verilog] memory_game.asm

Description: example for memory game in vhdl
Platform: | Size: 2048 | Author: ido | Hits:

[Other] uc_interface

Description: This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system. -This file provides an 8051 external data memory bus interface for CoolRunner CPLDs. This file contains the state machine to interface on the 8051 bus as well as the address registers, the address decode logic, and example control registers, status registers, data input registers, and data output registers. Interrupt logic is also included. Note that this code should be modified to meet the requirements of the system.
Platform: | Size: 4096 | Author: alex | Hits:

[VHDL-FPGA-Verilog] vhdl-code-for-Mc

Description: vhdl code for memory controller
Platform: | Size: 128000 | Author: JP | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[VHDL-FPGA-Verilog] Memory-ROMs-RAMs-and-Register-Files

Description: 有关memory的VHDL编码,已经过调制可用，是VHDL的基本编码。-VHDL code for memory.
Platform: | Size: 34816 | Author: 许舒敏 | Hits:
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