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[Other resource] 计数器：generate语句的应用

Description: VHDL语言应用实例,计数器的设计,用GENERATE语句实现-VHDL example, counter design, realization GENERATE statement
Platform: | Size: 1015 | Author: 刘杰 | Hits:

[VHDL-FPGA-Verilog] 计数器：generate语句的应用

Description: VHDL语言应用实例,计数器的设计,用GENERATE语句实现-VHDL example, counter design, realization GENERATE statement
Platform: | Size: 1024 | Author: 刘杰 | Hits:

[VHDL-FPGA-Verilog] frequency发生器

Description: vhdl语言实现的频率发生器，可以产生不同的频率-A frequency generator wirriten by VHDL, which can generate different frequecies.
Platform: | Size: 1024 | Author: xf | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[Other] mif

Description: 使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形-use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms
Platform: | Size: 1024 | Author: feng | Hits:

[VHDL-FPGA-Verilog] keyborad

Description: 一个8X8的矩阵键盘的VHDL文件,并且有长安键和短按键之分,即一共能做到128个键值,扫描用的时钟用1ms的就行了-A 8x8 matrix keyboard VHDL files and have Changan and short keys of key points, namely, to achieve a total of 128 keys, scanning with the clock used on the list of 1ms
Platform: | Size: 1024 | Author: 张风 | Hits:

[matlab] pn_generator

Description: PN码发生器的matlab程序，对于写vhdl代码有很重要得参考价值-PN code generator matlab procedures, write VHDL code for a very important reference value was
Platform: | Size: 1024 | Author: ylt | Hits:

[Other] testbench

Description: 32位除法器的测试程序， 由随机向量产生函数产生一组随机数 来验证计算书否正确-32 divider test procedures, by the random vector generated a set of functions to generate random numbers to verify whether the correct calculation of the book
Platform: | Size: 5120 | Author: 李春阳 | Hits:

[VHDL-FPGA-Verilog] vhdlgenerateofsentencegrammarapplication

Description: vhdl实验 计数器：generate语句的应用-Experimental VHDL Counter: generate statement application
Platform: | Size: 1024 | Author: 王天辉 | Hits:

[Communication-Mobile] FirGen_V1.1

Description: 產生你所需要的FIR濾波器，可以產生VHDL格式之源碼。-Have you need FIR filter, can generate VHDL source code format.
Platform: | Size: 368640 | Author: hcjian | Hits:

[Algorithm] VHDL

Description: 此代码可产生正弦波、三角波、正斜率拨、负斜率波波、矩形波五种波形-This code can generate sine wave, triangle wave, the slope is allocated, the negative slope of the ball, five rectangular-wave waveform
Platform: | Size: 1024 | Author: 刘三平 | Hits:

[MiddleWare] M_generate

Description: m序列产生编码，vhdl硬件实现用于实现调制解调-m sequence code generated, vhdl hardware implementation for the realization of modulation and demodulation
Platform: | Size: 247808 | Author: xiaohuaifeng | Hits:

[VHDL-FPGA-Verilog] Random_Number_generator

Description: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help
Platform: | Size: 35840 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D159

Description: 正弦波 发生器,VHDL的应用和处理,可以产生任意波形-Sine wave generator, VHDL applications and processing, can generate arbitrary waveform
Platform: | Size: 1731584 | Author: WBT | Hits:

[VHDL-FPGA-Verilog] DDS-320-modu

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。-320x240 screen using the design of experiments to run me generate sine wave, AM FM waveforms, sweep.
Platform: | Size: 1250304 | Author: hangyinli | Hits:

[GPS develop] generateCAcode

Description: gps C/A码生成 生成gps32颗卫星伪码，方便，经过测试-gps C/A code generation to generate pseudo-code satellites gps32, convenient and tested
Platform: | Size: 1024 | Author: zhangbo | Hits:

[VHDL-FPGA-Verilog] 2mxulie

Description: 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
Platform: | Size: 3072 | Author: 石一鸣 | Hits:

[VHDL-FPGA-Verilog] samlecode.vhdl

Description: THis code describes how to use the pwm singal generator and how to generate this using VHDL>
Platform: | Size: 17408 | Author: Jas | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk.
Platform: | Size: 4096 | Author: cccs | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:
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