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[Other resource] VHDL-ysw

Description: 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描述如下：-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows :
Platform: | Size: 2716 | Author: 杨仕伟 | Hits:

[source in ebook] VHDL_clock

Description: 数字钟 实现时、分、秒的显示和定时闹铃、整点报时等功能。-Realize digital clock hour, minute, second display and timing alarm, the whole point timekeeping functions.
Platform: | Size: 9216 | Author: 吴称光 | Hits:

[Other] GPSdecoder

Description: 采用状态机完成GPS串口信息GPRMC数据的解析，输出并行的年、月、日、时、分、秒信息，可直接移植。-State machine used to complete GPS information GPRMC serial data analysis, the output parallel year, month, day, hour, minute, second information, can be directly transplanted.
Platform: | Size: 1024 | Author: 杨启勇 | Hits:

[VHDL-FPGA-Verilog] clockVHDL

Description: 利用VHDL语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s-The use of VHDL language design digital clock, can be a normal hour, minute, second timing function, respectively, by 6 digital tube display 24h, 60min, 60s
Platform: | Size: 146432 | Author: 可爱 | Hits:

[VHDL-FPGA-Verilog] alarm

Description: 1．6个数码管动态扫描显示驱动 2．按键模式选择(时\分\秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求有闹钟定闹功能，时、分定闹即可，无需时、分、秒定闹。要求使用实验箱左下角的6个动态数码管(DS6 A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。-1.6 Digital control of dynamic scanning display driver 2. Mode selection button (when minutes and seconds) and adjust the control 3. Using hardware description language (or a combination of schematic diagram) design, minute and second counter module, key control state machine module, dynamic scanning display driver module, the top-level module. Required to make the alarm set function, the sub-set can make without hour, minute, second set downtown. Require the use of lower-left corner of the experimental box 6 dynamic digital tube (DS6 A ~ DS1A) shows hours, minutes, seconds request mode button and adjust the signal from the button after button after the Anti-shake deal with jack jumper.
Platform: | Size: 621568 | Author: xulina | Hits:

[assembly language] clock

Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
Platform: | Size: 11264 | Author: 金珊珊 | Hits:

[VHDL-FPGA-Verilog] Time

Description: 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
Platform: | Size: 382976 | Author: 张苏昕 | Hits:

[assembly language] EDAtest

Description: 关于数字钟的实现，用VHDL实现时，分，秒，的显示，并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
Platform: | Size: 171008 | Author: dulianjie1 | Hits:

[VHDL-FPGA-Verilog] clock_counter

Description: 一个简易的时分秒自加计数器，没有设置功能-hour-minute-second counter
Platform: | Size: 2048 | Author: Winson | Hits:

[VHDL-FPGA-Verilog] VHDL_clock

Description: VHDL数字钟设计程序 设计要求 基本要求： 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）；--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -
Platform: | Size: 71680 | Author: 苹果熊 | Hits:

[VHDL-FPGA-Verilog] VHDLDigitalClock

Description: 数字钟的VHDL语言实现基本功能，包括 1、24小时计数显示； 2、具有校时功能（时，分） ； 附加要求： 1、实现闹钟功能（定时，闹响）； -Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound)
Platform: | Size: 1024 | Author: xiezunzhong | Hits:

[VHDL-FPGA-Verilog] Displayer

Description: VHDL编写的针对八段数码管的显示译码电路。实现动态扫描输出小时、分钟和秒。是基于CPLD开发板设计的一个数字钟的一部分。-Programmed with VHDL.The decoding and displaying circuit for 8-segments displayer.It outputs the data of hour,minute and second in order with dynamic scaning method.It is one of my total 9 modules that are used to design a digital clock.
Platform: | Size: 150528 | Author: chzhsen | Hits:

[VHDL-FPGA-Verilog] RvsTime

Description: 用VHDL编写。数字钟校时电路，根据表示是否校时的输入引脚、是校正小时还是校正分钟的输入引脚决定校正状态。接受一个按钮的脉冲输入，每输入一个脉冲，被校正的时间增加1.与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.The time-revising circuit of a digital clock. Detect the inputs and decide if revise time, hour or minute. It recepts an impulse input from a key and the currently revised time will increase by 1 for each pushing of the key.
Platform: | Size: 118784 | Author: chzhsen | Hits:

[Other] VHDL-hour

Description: vhdl hour second minute
Platform: | Size: 2048 | Author: ben | Hits:

[VHDL-FPGA-Verilog] alarm

Description: VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for year, month, day, hour, minute and second separate proofreading, it corrected to standard time
Platform: | Size: 589824 | Author: yaonan | Hits:

[Software Engineering] clock____!

Description: The project is designed with the hour hand and the minute and the second time in the ISE software language. Vhdl written.
Platform: | Size: 1769472 | Author: Atefeh | Hits:

[Windows Develop] clock

Description: VHDL语言写的电子时钟，该数字电子钟能够实现时、分、秒计时功能；校准时和分的功能；校准时间时秒清零的功能；整点报时的功能；-written in VHDL，clock，count second，minute and hour
Platform: | Size: 3243008 | Author: 聪聪 | Hits:

[VHDL-FPGA-Verilog] VHDL-Multi-fuction-Clock

Description: 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-The design of a multi-function digital clock, required to display format for hours: Minutes: seconds, the whole point timekeeping and timer for 10 seconds, namely the whole point of 10 seconds before start timekeeping prompt, horn began to sound, until the whole point, in the whole point of 5 seconds the LED flashes, over the whole point, stop flicker. System clock to the clock module 10KHz, to get the 1Hz clock signal, the system must be 10000 times the system clock. Adjust the time of the keys with the key module S1 and S2, S1 adjust the hours, each press once, an hour to increase an hour, S2 to adjust the minutes, every time you press a minute, a minute. We also use the S8 button as the system clock reset, reset all display 00-00-00.
Platform: | Size: 7658496 | Author: 冯雨娴 | Hits:

[VHDL-FPGA-Verilog] szz

Description: 基于VHDL语言编写的EDA程序，可试小时分秒的自动进位，也可手动调时。-Based on Automatic carry EDA VHDL language program, you can try hour, minute and second, you can manually adjust the time.
Platform: | Size: 9750528 | Author: 齐天力 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: （1）24小时计时显示（时分秒）； （2）具有时间设置功能（时，分） ； （3）具有整点提示功能； （4）实现闹钟功能（定时，闹响）；((1) 24 hour time display (time, minute, second); (2) have time setting function (time and minute); (3) it has the function of whole point. (4) realize the alarm clock function (timing, noise);)
Platform: | Size: 4346880 | Author: Goddd | Hits:

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