Search - vhdl interleaver

[VHDL-FPGA-Verilog] cf_interleaver2

Description: interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials are intertwined
Platform: | Size: 360448 | Author: 陈朋 | Hits:

[Other] 3GPPjiaozhi

Description: 3Gpp 25.212 交织器交织深度1024进行行内行间交织-3Gpp 25.212 intertwined depth interleaver 1,024 firms conducted between experts intertwined
Platform: | Size: 2048 | Author: 李春晖 | Hits:

[VHDL-FPGA-Verilog] suij

Description: 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
Platform: | Size: 2048 | Author: 孟旭 | Hits:

[GDI-Bitmap] verilog_interleave1

Description: 里面是5个关于交织器的源代码，有兴趣的可以下来学习一下-There is a 5 on the interleaver of the source code, are interested in learning what can be down
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[VHDL-FPGA-Verilog] veriloginterleave2

Description: 交织器的在5个源代码，:-) 对学习交织器真的很有用的啊 -Interleaver in 5 source code, :-) learning interleaver ah really useful
Platform: | Size: 11264 | Author: 吴雨彤 | Hits:

[Communication-Mobile] jiaozhiqi_fpga

Description: 实现一个用于CDMA2000系统的短帧交织器,计算比较了12*16,13*15,14*14三种交织形式的性能!-CDMA2000 system for the realization of a short interleaver frame, the calculation compares the 12* 16,13* 15:14* 14 three intertwined forms of performance!
Platform: | Size: 2048 | Author: 刘思成 | Hits:

[VHDL-FPGA-Verilog] interleave

Description: 数据交织器 verilog HDL源文件-Data interleaver verilog HDL source file
Platform: | Size: 100352 | Author: 长空 | Hits:

[VHDL-FPGA-Verilog] 4_31

Description: 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
Platform: | Size: 834560 | Author: 谢建伟 | Hits:

[VHDL-FPGA-Verilog] interleaver-vhdl

Description: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
Platform: | Size: 1024 | Author: cab | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
Platform: | Size: 1024 | Author: chenxiaoming | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
Platform: | Size: 27648 | Author: 尚龙 | Hits:

[Communication] Turbo

Description: 利用3GPP交织器和LTE交织器完成turbo码的仿真并做比较，不同解码算法的比较-Using 3GPP Interleaver and complete LTE interleaver turbo code simulation and comparison, a comparison of different decoding algorithms
Platform: | Size: 112640 | Author: 老五 | Hits:

[Program doc] DVB

Description: DVB系统中交织器和解交织器设计的FPGA实现-DVB system, the reconciliation Interleaver Interleaver design FPGA implementation
Platform: | Size: 708608 | Author: 程钢 | Hits:

[Communication] address_gen

Description: 卷积交织的地址生成器，通过编译，很好的代码，珍藏-Convolutional Interleaver address generater
Platform: | Size: 3072 | Author: 魏强 | Hits:

[Other] FPGA_interleaver

Description: 这是一个基于FPGA的交织器的VHDL源代码-This is an FPGA-based interleaver of the VHDL source code for
Platform: | Size: 120832 | Author: xx | Hits:

[VHDL-FPGA-Verilog] jiaozhiqi

Description: 是Turbo码交织器的VHDL设计与仿真的文献-Is the Turbo Code Interleaver Design and Simulation of VHDL literature
Platform: | Size: 765952 | Author: 郑国 | Hits:

[VHDL-FPGA-Verilog] interweave_1

Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Platform: | Size: 36864 | Author: 李修函 | Hits:

[VHDL-FPGA-Verilog] interleaver

Description: vhdl code for interleaver
Platform: | Size: 1024 | Author: aruna | Hits:

[Documents] 基于VHDL卷积交织器的设计与实现

Description: 基于VHDL卷积交织器的设计与实现(1)(Design and implementation of convolution Interleaver Based on VHDL)
Platform: | Size: 214016 | Author: 大的幅度 | Hits:

« 12 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] cf_interleaver2

[Other] 3GPPjiaozhi

[VHDL-FPGA-Verilog] suij

[GDI-Bitmap] verilog_interleave1

[VHDL-FPGA-Verilog] veriloginterleave2

[Communication-Mobile] jiaozhiqi_fpga

[VHDL-FPGA-Verilog] interleave

[VHDL-FPGA-Verilog] 4_31

[VHDL-FPGA-Verilog] interleaver-vhdl

[Other] interleaver

[VHDL-FPGA-Verilog] interleaver

[VHDL-FPGA-Verilog] interleaver

[Communication] Turbo

[Program doc] DVB

[Communication] address_gen

[Other] FPGA_interleaver

[VHDL-FPGA-Verilog] jiaozhiqi

[VHDL-FPGA-Verilog] interweave_1

[VHDL-FPGA-Verilog] interleaver

[Documents] 基于VHDL卷积交织器的设计与实现

CodeBus www.codebus.net