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[VHDL-FPGA-Verilog] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] elock.vhdl.pdf

Description: 一种基于VHDL的电子密码锁论文设计，有部分代码，可以下来作为参考。-A VHDL-based electronic locks thesis design, have some code that can be down as a reference.
Platform: | Size: 368640 | Author: 李里 | Hits:

[Other] MultipleNumbersCalculator

Description: Multiple Numbers Calculator (source code and LAB notes)
Platform: | Size: 1017856 | Author: eknngx | Hits:

[Video Capture] vedio_collection

Description: 在这个压缩包里，包含了关于视频采集知识的一些基本的介绍。并且在里面还包含了一个基于spartan-3E的视频采集实验-The compressed pack contains some fundemental introdutions about video collections .What s more ,there is a referenced lab on vedio collection which is based on spartan-3E!
Platform: | Size: 2871296 | Author: 艾巍 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 《VHDL程序设计教程》光盘使用说明 本光盘是邢建平和曾繁太所著《VHDL程序设计教程》一书的配书光盘。本光盘的著作权归作者所有。 清华大学出版社享有该光盘的中文简体版专有出版权。 本光盘包括如下目录： “e_teaching_vhdl”--CAI教学材料 包含全套的PowerPoint文件，可以直接用于教学，具体请参见该目录中的index.pps文件说明。 共包含前言、第一章到第六章的教学文件。目前包含的为中文版辅助材料。最新版本将在下面给出 的“www.its.sdu.edu.cn”网站不定期更新。 “vhdl fortextboot”--教程代码 包含本书教程例子的所有代码。 “vhdl for lab”--教程实验部分代码 包含本书教程实验部分所有代码。 “vhdl solutions”--教程习题参考解答 包含本书教程习题参考解答的文档。 “class music”--课间休息音乐欣赏 包含课间休息的中外音乐欣赏。 -good
Platform: | Size: 2779136 | Author: xiong | Hits:

[Software Engineering] 13105886-vhdl-lab-programs

Description: vhdl programme on lfsr
Platform: | Size: 289792 | Author: rahul | Hits:

[Multimedia program] matladfilefordecom

Description: mat lab codes for watermarking
Platform: | Size: 13312 | Author: govindu | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 本实验在实验室实现了对于简易的乒乓球游戏的模拟，以发光二极管的移动来模拟乒乓球的移动，转向表示击球，并实现积分。-In this study, achieved in the lab for a simple table tennis game simulation, in order to light-emitting diodes to simulate the movement of table tennis movement, turning that ball and achieve integration.
Platform: | Size: 325632 | Author: wanjiabao | Hits:

[Other] WatchForLab

Description: This was the first lab assigmnet in the course CPU Architecture, creat a basic watch
Platform: | Size: 1140736 | Author: zarbob | Hits:

[VHDL-FPGA-Verilog] experiment5_1

Description: VHDL实验5，七段数码显示译码器设计。1）用VHDL设计7段数码管显示译码电路，并在VHDL描述的测试平台下对译码器进行功能仿真，给出仿真的波形。-VHDL Lab 5, Seven-Segment Display Decoder. 1) design using VHDL 7 segment LED display decoder circuit, and the VHDL description of the decoder under test platform for functional simulation, the simulation waveforms.
Platform: | Size: 143360 | Author: 童长威 | Hits:

[Other] lab

Description: VHDL ebook for beginner
Platform: | Size: 306176 | Author: hue | Hits:

[Embeded-SCM Develop] VideoLoopback

Description: VHDL写的完整的图像采集与处理的程序，经实验，完全调通 -vhdl program about the picture process,and it is doing well in the lab.
Platform: | Size: 658432 | Author: eingates | Hits:

[Industry research] Verilog+lab+3+-+HTN+lab+2

Description: a lab by vhdl, let discover and enjoy it now
Platform: | Size: 1666048 | Author: huỳ nh an | Hits:

[VHDL-FPGA-Verilog] VERILOG_VLSI_LAB_MANUAL

Description: VHDL Lab Manual useful for lab purpose
Platform: | Size: 1921024 | Author: Vinodh | Hits:

[VHDL-FPGA-Verilog] lab

Description: VHDL Lab manual useful for experiment purpose
Platform: | Size: 1001472 | Author: Vinodh | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] 50973937-VHDL-Report

Description: Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For some problems, more than one solution is presented. Second, a conclusion is made about the main confronts that I have faced. Finally, a list of refrences is included. Regarding the software tools, ISE 9.2i Design suite is used. However, due to bugs introduced with ISE Simulator 9.2i. I have upgradted to the next version ISE Design suite 10.1. Sometimes, ModelSim is also used for checking some codes. With respect to FPGA, All the codes are synthesized and implementedsome of them- for Spartan3an xc3s700AN. The same kind of FPGA we have within our lab
Platform: | Size: 1016832 | Author: phitoan | Hits:

[VHDL-FPGA-Verilog] vhdl1

Description: vhdl lab for using labarories
Platform: | Size: 3340288 | Author: mustafa | Hits:

[e-language] vhdl-lab-report

Description: vhdl实验报告，关于4位选择器，在maxplusII下运行-vhdl lab report
Platform: | Size: 3072 | Author: 宋兵 | Hits:

[Other] LAB

Description: SAM VHDL编码，包括数据选择器，加法器，简易逻辑电路，有限状态机等(FSM SAM ALU and many other different parts)
Platform: | Size: 6144 | Author: TimeParaodgs | Hits:
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