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[Embeded-SCM Develop] moore

Description: Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.-Moore-type state machine design, based on VHDL. Be able to read and write cycle of microprocessors, corresponding memory output enable WE write and read enable signal OE.
Platform: | Size: 25600 | Author: weixiaoyu | Hits:

[VHDL-FPGA-Verilog] MOORE

Description:
Platform: | Size: 190464 | Author: wang | Hits:

[VHDL-FPGA-Verilog] STATE1

Description: VHDL源代码，莫尔型状态机，使用VHDL语言编写-VHDL source code, Moore type state machine, the use of VHDL language
Platform: | Size: 3072 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] STATE2

Description: VHDL源代码，使用VHDL语言编写，莫尔型状态机-VHDL source code, the use of VHDL language, Moore type state machine
Platform: | Size: 3072 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] STATE5

Description: VHDL源代码程序，使用VHDL语言编写，米勒，莫尔型状态机-VHDL source code, the use of VHDL language, Miller, Moore type state machine
Platform: | Size: 3072 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[VHDL-FPGA-Verilog] diyabiao

Description: moore状态机~~~ 用vhdl语言实现-moore state machine ~ ~ ~ using VHDL language
Platform: | Size: 14336 | Author: 黎明 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 状态机及其VHDL设计,详细介绍了状态机的基本结构、功能和分类，以及有限状态机的一般设计思路与方法、状态机编码方案的恰当选取、Moore和Mealy状态机的本质区别及设计实现-State machine and the VHDL design, described in detail the basic structure of state machines, function and classification, as well as finite state machine of the general design ideas and methods, state machine to select the appropriate coding schemes, Moore and Mealy state machine and design of the essential difference between the achievement of
Platform: | Size: 72704 | Author: 史东寒 | Hits:

[VHDL-FPGA-Verilog] zhuangtaiji

Description: 十种状态机例子（VHDL）包括米勒型和莫尔型的状态机。-Dozens of examples of state machine (VHDL), including Miller and Moore type state machine.
Platform: | Size: 5120 | Author: 张先锋 | Hits:

[VHDL-FPGA-Verilog] vhdl_model

Description: VHDL实例，各个方面均有，基本语法，状态机，汉明码，寄存器，步进电机控制器，表决器，多路选择器，译码器-VHDL model,include: basic grammer,moore mealy state machine,register,counter,multi,decoder,et..
Platform: | Size: 50176 | Author: Rainer | Hits:

[VHDL-FPGA-Verilog] CIC_Moore

Description: It is a complete project of Cache Interface Controller programmed in VHDL using the logic of Moore State Machine
Platform: | Size: 361472 | Author: Mr J | Hits:

[VHDL-FPGA-Verilog] VHDL2

Description: 一个关于VHDL的moore状态机的程序，让你了解状态机的运行方法。-One on the moore state machine VHDL procedures so that you understand the operation of the state machine approach.
Platform: | Size: 1024 | Author: wyb | Hits:

[VHDL-FPGA-Verilog] state_machine

Description: 摩尔状态机的程序，超经典的，用VHDL写的，初学者可以参考-Moore state machine program, ultra classic, written with VHDL, beginners can refer to
Platform: | Size: 1024 | Author: wyp | Hits:

[VHDL-FPGA-Verilog] State_Machine

Description: 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state machine.
Platform: | Size: 1551360 | Author: baoguocheng | Hits:

[MiddleWare] MOORE_state

Description: MOORE状态机 vhdl描述的moore型状态机 在QUARTUS上的仿真与实现-moore state Machine
Platform: | Size: 292864 | Author: yms | Hits:

[VHDL-FPGA-Verilog] s_machine

Description: 单进程Moore状态机，st0到st4的五个不同状态间的转换。性能良好的同步时序逻辑模块； 与VHDL的其他描述方式相比，状态机的VHDL表述丰富多样、程序层次分明，结构清晰，易读易懂-Single process Moore state machine, st0 to st4 five conversion between different states. Good performance of synchronous sequential logic module Compared with other VHDL description method, the state machine to diverse VHDL description, procedures, distinct, the structure is clear, readable and easy to understand
Platform: | Size: 338944 | Author: 杜雨峰 | Hits:

[VHDL-FPGA-Verilog] code_lock_vhdl

Description: 在ISE环境下用vhdl写的一个密码锁程序。下载到xilinx 公司的 spartan6 的板子上验证过的，也有仿真代码。主要就是几个状态之间的转换，用了一个moore状态机。-In the ISE environment using vhdl to write a lock program. Downloaded to the board spartan6 xilinx' s proven, there are simulation code. Mainly the conversion between several states, with a moore state machine.
Platform: | Size: 846848 | Author: 高转转 | Hits:

[Other] kebenchengxu

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, synchronous counter, sequence detector design. Sequence signal generator, general state machine etc..)
Platform: | Size: 40960 | Author: girl_lily | Hits:

[VHDL-FPGA-Verilog] 1

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 priority encoder, 8 choose 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital frequency meter, digital clock, sequence detector design, general state machine etc..)
Platform: | Size: 453632 | Author: zidting | Hits:

[VHDL-FPGA-Verilog] 2

Description: VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字时钟，序列检测器的设计，一般状态机等等。(VHDL code, some textbooks for small programs. It includes 3 line -8 line decoder, 4 selector 1 selector, 6 elevator, 8 line -3 encoder, 8 line -3 line priority encoder, 8 select 1, BCD-7 segment display decoder truth table, half adder, Moore state machine, digital clock, sequence detector design, general state machine and so on.)
Platform: | Size: 454656 | Author: zidting | Hits:
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