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[Other resource] CUS_SPI-VHDL

Description: 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Platform: | Size: 3875 | Author: 藏瑞 | Hits:

[Other resource] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10174 | Author: 孟轲敏 | Hits:

[VHDL-FPGA-Verilog] EDAchuzuchejijia

Description: 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example, the simulation methods and timing diagrams, is a good example to learn VHDL.
Platform: | Size: 339968 | Author: bkd | Hits:

[OS Develop] ARM_00_OS

Description: 看看ARM菜鸟在ARM7上写的操作系统——ARM圈圈操作系统 最近在ADuC7027上写了一个ARM_00_OS，头都写晕了，发上来给大家一起来看看。 任务按优先级调度，如果处于就绪态且优先级最高的任务有两个或更多，则按时间片轮循调度。 支持任务创建、任务删除、内存分配、简单的消息、简单的设备管理、CPU及内存等使用统计等功能。 任务可处于ARM模式或THUMB模式，在创建任务时，要指定任务所处于的模式。 从这里下载整个文件包：http://blog.21ic.com/more.asp?name=computer00&id=16341 -look at birdie in ARM ARM7 written in the operating system-- the operating system ARM circle recently in ADu C7027 write a ARM_00_OS, write head dizzy, deputy undersecretary for everyone to see. Tasks according to priority scheduling, in place if the state but the highest priority tasks of two or more, according to the time-Round Robin scheduling. Support mission to create, delete tasks, memory allocation, the simple information, a simple device management, CPU and memory usage statistics capabilities. At tasks THUMB ARM model or models in the creation mandate, the mandate should be designated at a model. From here to download the whole package : http :// blog.21ic.com/more.asp name = computer00
Platform: | Size: 360448 | Author: Computer00 | Hits:

[VHDL-FPGA-Verilog] arith_lib_cadence

Description: Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
Platform: | Size: 81920 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] CUS_SPI-VHDL

Description: 此为VHDL的SPI通信代码，全部在一个压缩包中，请仔细阅读后再使用．-this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Platform: | Size: 4096 | Author: 藏瑞 | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[source in ebook] C_9

Description: 100个经典vhdl编程实例， 第1例 带控制端口的加法器 第2例 无控制端口的加法器 第3例 乘法器 第4例 比较器 第5例 二路选择器 第6例 寄存器 第7例 移位寄存器 第8例 综合单元库 第9例 七值逻辑与基本数据类型 第10例 函数 第11例 七值逻辑线或分辨函数 第12例 转换函数 第13例 左移函数 第14例 七值逻辑程序包 第15例 四输入多路器...... -100 vhdl classical programming examples, No. 1 is the control port Adder first two cases of uncontrolled port Adder No. 3 Multiplier first four cases compared with the first five cases 2 Lu choice for the first six cases Register No. 7 cases shift register first eight cases consolidated for the first module nine cases seven-valued logic and basic data types No. 10 No. 11 cases function seven-valued logic function or defective Line No. 12 conversion functions No. 13 bits function section 14 cases 7 logic package No. 15 cases four multi-input devices ......
Platform: | Size: 336896 | Author: | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] VHDL_1

Description: 使用硬體描述語言HDL 設計硬體電路，台湾人写的PPT讲义，非常不错。VHDL硬件设计入门学习。VHDL基本語法架構，VHDL的零件庫(Library)及包裝(Package)等内容。-The use of hardware description language HDL design hardware circuits, Taiwan, written by PPT notes, very good. VHDL hardware design entry-learning. VHDL basic grammar structure, VHDL Parts Library (Library) and packaging (Package) and so on.
Platform: | Size: 18432 | Author: WeimuMa | Hits:

[VHDL-FPGA-Verilog] arith_lib-1.0

Description: 国外的复杂算术运算包，包括SD和RNS等复杂运算，效率很高！-Complex arithmetic operations abroad package, including SD and RNS, such as the complexity of computing and efficient!
Platform: | Size: 246784 | Author: cai | Hits:

[VHDL-FPGA-Verilog] 100vhdl_examples

Description: VHDL100个例子,由于其他原因压缩包内只有93个,如果需要完整的请联系.从最简单的加法到最后的SPARC芯片的源描述.-VHDL100 example, compressed package for other reasons, only 93, if you need to complete please contact. From the most simple addition to the final description of the source of SPARC chip.
Platform: | Size: 235520 | Author: 陈夕 | Hits:

[Other Embeded program] crc16

Description: 16位的CRC校验函数包。符合ccitt标准，查表法校验，速度快。节省CPU时间。值得一看！-16 The CRC checksum function package. Consistent with the CCITT standards, look-up table method validation, fast. Save CPU time. Worth a visit!
Platform: | Size: 1024 | Author: cumt | Hits:

[assembly language] VHDL

Description: 包内共有六个源代码，每个文本的名称为其功能名称，用汉语拼音拼写。-A total of six package source code, the name of each text for its function name, using Pinyin spelling.
Platform: | Size: 2048 | Author: fyy | Hits:

[VHDL-FPGA-Verilog] vhdl-arm-core

Description: 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used to open quartus2 simulation software.
Platform: | Size: 41984 | Author: 杨帆 | Hits:

[VHDL-FPGA-Verilog] VHDLprogram

Description: VHDL的程序包，包括LED控制，LCD控制、DAC0832接口电路、URAT、FSK\PSK\MASK调制、波形发生器等。适合工程参考-VHDL package, including the LED control, LCD control, DAC0832 Interface Circuit, URAT, FSK \ PSK \ MASK modulation, such as waveform generator. Reference for the project
Platform: | Size: 1133568 | Author: | Hits:

[VHDL-FPGA-Verilog] uart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[Other] VHDL-Package-Quick-Reference

Description: Instruction set of vhdl
Platform: | Size: 36864 | Author: leo_bahia | Hits:

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination of the 3-8 decoder logic device)
Platform: | Size: 10240 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] 按键去抖电路VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 29696 | Author: lixilin | Hits:
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