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[DSP program] CA-vfdl

Description: GPS C/A码 发生器 LFSR 源代码 VHDL 语言-GPS C/A code generator LFSR VHDL source code
Platform: | Size: 1024 | Author: wuhao | Hits:

[VHDL-FPGA-Verilog] serial_ppga

Description: 异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control
Platform: | Size: 199680 | Author: 孙洪亮 | Hits:

[VHDL-FPGA-Verilog] simple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] AsynCommCtrl

Description: 基于VHDL的串行异步通信电路的设计 包括串行发送器，异步接收器，以及控制器 vhdl-VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
Platform: | Size: 4096 | Author: 飘来的南风 | Hits:

[Program doc] 109341_

Description: Design, Implementation and Testing of a Digital Baseband Receiver for Spread Spectrum Telesensing (VHDL)-Design, Implementation and Testing of a Digital Baseba nd Receiver for Spread Spectrum Telesensing (V HDL)
Platform: | Size: 467968 | Author: 山姆大叔 | Hits:

[RFID] codeacq

Description: 扩频接收机设计实例,vhdly源代码!大家下载下来吧,在ise中调试通过-Spread spectrum receiver design example, vhdly source code! Everyone download it, in the ise of debugging through
Platform: | Size: 2048 | Author: 萧勇 | Hits:

[VHDL-FPGA-Verilog] uart_for_MCU

Description: 用VHDL为MCU编写的可用UART-通用异步收发器程序-Using VHDL for the MCU can be used to prepare the UART-Universal Asynchronous Receiver Transmitter procedures
Platform: | Size: 1024 | Author: pc repair | Hits:

[VHDL-FPGA-Verilog] usart_verilog

Description: 通用串行异步收发器8251的Verilog HDL源代码.doc-Universal Serial Asynchronous Receiver Transmitter 8251 the Verilog HDL source code. Doc
Platform: | Size: 15360 | Author: 赵国柱 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Platform: | Size: 3072 | Author: ditto | Hits:

[VHDL-FPGA-Verilog] bit-catchingupFPGA

Description: 本文是在FPGA下，实现的有关接收机位同步电路文章，介绍了实现的方法等。-This article is in the FPGA, the realization of the receiver bit synchronization circuit article introduces the realization of the methods.
Platform: | Size: 205824 | Author: youyou | Hits:

[Communication] Mov9

Description: 本工程实现的是9位义位与串并变换模块 具体工作过程是： 在时钟CLK的上升沿触发下，从inp端输入接收m序列，按顺序inp->A9->A8->...->A0进行意味，同时把A9，A8，...A0的输出分别给B9，B8，B7,...从而完成串并转换的功能。Q端的信号取自A0的输出短，作为一位4位后的串行m序列信号。 clk为输入时钟信号；inp为接收序列信号输入；Q为串行序列输出；B0~B3为四位并行序列输出。-Realize this project is 9 Sememe transform module with the string and the specific work process is: In the rising edge of CLK clock trigger from inp input receiver m sequence, according to the order of inp-
Platform: | Size: 247808 | Author: youyou | Hits:

[Com Port] UARTchuli

Description: UART 处理的是并行数据转换为串行信号和串行信号转换为并行数据。现有的时钟不精确,这就需要用一个远高于波特率的本地时钟信号对输入信号不断采样,以不断让接收器与发送器保持同步。-UART to handle is the parallel data into a serial signal and serial signal is converted to parallel data. Existing imprecise clock, which requires a much higher than the baud rate of the local clock signal for sampling the input signal continuously to continuously allow the receiver to maintain synchronization with the transmitter.
Platform: | Size: 1024 | Author: xuye | Hits:

[VHDL-FPGA-Verilog] VHDL_infrared_receive

Description: VHDL程序，实现红外接收，解码，功能可扩展，入门者用-VHDL procedures realize infrared receiver, decoding, feature scalable, beginners to use
Platform: | Size: 2048 | Author: 小猪 | Hits:

[Other] EDAandVHDL

Description: EDA技术与VHDL 实用电路设计 步进电机和直流电机控制，VGA显示控制器设计，存储示波器设计，通用异步收发器设计，频率相位计设计，DDS设计，-EDA technology and VHDL practical circuit design stepper motors and DC motor control, VGA display controller design, storage oscilloscope design, universal asynchronous receiver design, frequency, phase meter design, DDS design,
Platform: | Size: 1571840 | Author: viet | Hits:

[VHDL-FPGA-Verilog] Receiver

Description: 该程序是整个OFDM接收机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。-The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.
Platform: | Size: 1497088 | Author: zhougongming | Hits:

[VHDL-FPGA-Verilog] gps_tracking

Description: 澳大利亚新南威尔士大学研究的GPS接收机的FPGA跟踪模块的.v程序，包括载波跟踪环路、码跟踪环路、通道累加等模块。-The University of New South Wales, Australia, the study of the FPGA tracking GPS receiver module. V procedures, including the carrier tracking loop, code tracking loop, the channel accumulation modules.
Platform: | Size: 14336 | Author: Jerry | Hits:

[Communication-Mobile] Receiver

Description: OFDM通信系统接收端完整verilog代码-OFDM communication system receiver complete verilog code
Platform: | Size: 1497088 | Author: 王练 | Hits:

[VHDL-FPGA-Verilog] Spread-Spectrum-Receiver-code

Description: 基于FPGA的扩频接收机（直扩）vhdl编写的，最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
Platform: | Size: 361472 | Author: 赵童 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: uart rs232 receiver and transmiter
Platform: | Size: 4096 | Author: franek kimono | Hits:

[VHDL-FPGA-Verilog] all-digital-fm-receiver

Description: all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
Platform: | Size: 1545216 | Author: Rahul | Hits:
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