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[VHDL-FPGA-Verilog] serial

Description: 串行口数据传输实验，vhdl源代码，完成信号发生，串并转换，检测电路-Serial port data transmission experiment, vhdl source code, complete the signal occurred, SERDES, detection circuit
Platform: | Size: 1024 | Author: yew | Hits:

[VHDL-FPGA-Verilog] elecfans.comMPSK

Description: 用VHDL实现的基带信号进行MPSK调制 及串并转换-Achieved using VHDL baseband MPSK signal modulation and SERDES
Platform: | Size: 2048 | Author: 王黎波 | Hits:

[MPI] readme_vhd

Description: VHDL串并转换源程序，可以实现信号在串行和并行间的转换。-SERDES VHDL source code, you can achieve signal at between serial and parallel conversion.
Platform: | Size: 1024 | Author: kimli | Hits:

[VHDL-FPGA-Verilog] LVDS_Serdes_list_FPGA1

Description: FPGA之间的LVDS传输，采用serdes接口，传输速率达到400m-LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
Platform: | Size: 14338048 | Author: linpingping | Hits:

[VHDL-FPGA-Verilog] s2p

Description:
Platform: | Size: 1024 | Author: wangdali | Hits:

[USB develop] CPLD_USB

Description: ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特 点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速 USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-based company introduced the CPLD chip ATF1508AS SERDES design and high-speed USB and its application in high-speed high-precision data acquisition system
Platform: | Size: 186368 | Author: 简单 | Hits:

[VHDL-FPGA-Verilog] MAIN_TX_V10

Description: 8路视频光端机的VHDL源码，此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。-8-channel video PDH in VHDL source code
Platform: | Size: 290816 | Author: tr | Hits:

[VHDL-FPGA-Verilog] MAIN_RX_V10

Description: 8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
Platform: | Size: 1088512 | Author: tr | Hits:

[VHDL-FPGA-Verilog] TX

Description: 1路视频光端机的发射端，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-The launch of a video PDH client, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 103424 | Author: tr | Hits:

[VHDL-FPGA-Verilog] RX

Description: 1路视频光端机的接收端，VHDL源码，使用全FPGA芯片的硬件，内建解帧、时钟、DESERDES-PDH a video of the receiving end, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 104448 | Author: tr | Hits:

[VHDL-FPGA-Verilog] F7-2VT-1DR

Description: 2路视频光端机的，VHDL源码，使用全FPGA芯片的硬件，内建成帧、时钟、SERDES-2-way video PDH' s, VHDL source code, use the whole FPGA chip hardware, built-in framing, clock, SERDES
Platform: | Size: 461824 | Author: tr | Hits:

[Other] LPM

Description: LPM 是参数可设置模块库Library of Parameterized Modules 的英语缩写，Altera 提供的 可参数化宏功能模块和LPM 函数均基于Altera 器件的结构做了优化设计。在许多实用情况 中，必须使用宏功能模块才可以使用一些Altera 特定器件的硬件功能。例如各类片上存储 器、DSP 模块、LVDS 驱动器、嵌入式PLL 以及SERDES 和DDIO 电路模块等等。这些可 以以图形或硬件描述语言模块形式方便调用的宏功能块，使得基于EDA 技术的电子设计的 效率和可靠性有了很大的提高。设计者可以根据实际电路的设计需要，选择LPM 库中的适 当模块，并为其设定适当的参数，就能满足自己的设计需要，从而在自己的项目中十分方 便地调用优秀的电子工程技术人员的硬件设计成果。 LPM 功能模块内容丰富，每一模块的功能、参数含义、使用方法、硬件描述语言模块 参数设置及调用方法都可以在QuartusⅡ中的Help 中查阅到，方法是选择“Help”菜单中 的“Megafunctions/LPM”命令。-LPM
Platform: | Size: 1526784 | Author: lidandan | Hits:

[Program doc] Multi_Gigabit_transceiver

Description: A Multi-Gigabit Transceiver (MGT) is a SerDes capable of operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data communications because they can run over longer distances, use fewer wires, and thus have lower costs than parallel interfaces with equivalent data throughput.
Platform: | Size: 466944 | Author: cidadeus | Hits:

[VHDL-FPGA-Verilog] SERDES

Description: 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

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