Search - vhdl simple UART

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[Other resource] 一个简单的UART DL : 0: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Update : 2008-10-13 Size : 3.57kb Publisher : 陈旭
[VHDL-FPGA-Verilog] 一个简单的UART DL : 1: 采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
Update : 2025-02-17 Size : 3kb Publisher : 陈旭
[VHDL-FPGA-Verilog] VHDL_processor DL : 0: 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Update : 2025-02-17 Size : 725kb Publisher : 赵康
[VHDL-FPGA-Verilog] ISE_uart DL : 0: 自己在ISE下用VHDL写的UART，简单，易懂-in ISE using VHDL was the UART, simple, understandable
Update : 2025-02-17 Size : 915kb Publisher : sk
[VHDL-FPGA-Verilog] uart0vhdl DL : 0: vhdl实现fpga和PC机的简单通信(发送),-vhdl achieve fpga and PC simple communication (transmission),
Update : 2025-02-17 Size : 1kb Publisher : 刘音
[Linux-Unix] UART DL : 0: 自己用VHDL写的一个串口程序，调试成功，并且用到了项目中，希望初学者可以借鉴下-Their use VHDL to write a serial program, debug the success of the project and used in the hope that beginners can learn from the next
Update : 2025-02-17 Size : 299kb Publisher : yanglei
[VHDL-FPGA-Verilog] UART DL : 0: 串行接口UART的用VHDL语言的简单实现，希望对大家有帮助-UART serial interface of the VHDL language with the simple realization, in the hope that everyone has to help
Update : 2025-02-17 Size : 3kb Publisher : wangyd
[VHDL-FPGA-Verilog] UART1 DL : 0: 自己编写的UART模块用VHDL实现，简单实用-I have written UART modules use VHDL realization of simple and practical
Update : 2025-02-17 Size : 3kb Publisher : L
[VHDL-FPGA-Verilog] uart_exam DL : 0: VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
Update : 2025-02-17 Size : 1kb Publisher : jimmy
[VHDL-FPGA-Verilog] miniUart DL : 0: 一个简单的uart的VHDL描述，希望对大家有点帮助-A simple UART in VHDL description, I hope all of you a little help
Update : 2025-02-17 Size : 19kb Publisher : 肖冠兰
[VHDL-FPGA-Verilog] UART DL : 0: 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Update : 2025-02-17 Size : 574kb Publisher : 李欣
[VHDL-FPGA-Verilog] miniuart.tar DL : 0: 用VHDL描述的简单UART接口，能正确实现简单的功能-VHDL description with a simple UART interface
Update : 2025-02-17 Size : 6kb Publisher : elvis
[Other] uart_test_ok_921 DL : 0: 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
Update : 2025-02-17 Size : 371kb Publisher : wmd
[VHDL-FPGA-Verilog] uart-vhdl-testbench DL : 0: simple uart vhdl behavioural model (package) vhdl testbench example
Update : 2025-02-17 Size : 2kb Publisher : Mark
[Embeded-SCM Develop] UART DL : 0: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Update : 2025-02-17 Size : 44kb Publisher : sandeep
[Com Port] RS232 DL : 0: simple example for uart on fpga
Update : 2025-02-17 Size : 698kb Publisher : Jay
[VHDL-FPGA-Verilog] UART DL : 0: This vhdl code has a simple implementation of an UART receiver. This code was generated march 2011 as a universuty project
Update : 2025-02-17 Size : 1kb Publisher : plcpe
[VHDL-FPGA-Verilog] uart DL : 0: 一个简单的UART程序，包括接收，发送，波特率产生-A simple UART program, including receiving, sending, baud rate generation
Update : 2025-02-17 Size : 5kb Publisher : 洪琳琅
[VHDL-FPGA-Verilog] RS232-Simple DL : 0: A simple UART example for reference in VHDL.
Update : 2025-02-17 Size : 70kb Publisher : Cong
[VHDL-FPGA-Verilog] uart DL : 0: VHDL编写的UART异步串行通信接口程序，，，经过仿真验证，简单易懂-VHDL prepared UART asynchronous serial communication interface program, through simulation, simple,,,,,
Update : 2025-02-17 Size : 1.58mb Publisher : 周健

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