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[Other resource] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233299 | Author: 杰轩 | Hits:

[Other resource] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 998 | Author: 罗兵武 | Hits:

[Other resource] pulse-VHDL

Description: 可控脉冲产生ＶＨＤＬ程序 开发软件ＩＳＥ，程序通过了器件后仿真并在芯片ＸＣ９５７２中实现了-controllable pulse generated VHDL ISE software development procedures, procedures adopted after the simulation devices and chips to achieve the XC9572
Platform: | Size: 43916 | Author: 林海 | Hits:

[Embeded-SCM Develop] digitalsecondwatch(VHDL)

Description: 应用ＶＨＤＬ、ＣＰＬＤ、ＥＤＡ开发软件设计数字系统,能够显著增强设计的灵活性,提高产品的性能,减轻设计的工作量,缩短设计周期。传统的“固定功能集成块+连线”的设计方法正逐步地缩小应用范围,而基于芯片的设计方法正成为电子系统设计的主流。ＶＨＤＬ语言、ＣＰＬＤ/ＦＰＧＡ、ＥＤＡ开发软件已成为设计复杂数字电路系统的重要工具。-use VHDL, CPLD, EDA software to design digital system, can significantly improve design flexibility, improve product performance, reduce the workload designed to shorten the design cycle. The traditional "fixed-function IC Alliance," The design method is to gradually narrow the scope of application, For the chip design is becoming electronic systems design. VHDL, CPLD / FPGA, EDA software development has become a complex digital circuit design system an important tool.
Platform: | Size: 1451 | Author: laiweidong | Hits:

[MultiLanguage] VHDL-3fenpindianlu

Description: 该程序用VHDL硬件描述语言编写而成,已调试通过,程序运行后可实现三分频,这样就用软件设计代替了硬件设计,方便,稳定,不需要硬件调试!-the procedures used VHDL hardware description language, prepared debugging has passed, After running third frequency can be realized, so software designed to replace the hardware design, convenience, stability, no hardware debugging!
Platform: | Size: 2291 | Author: sdcsadf | Hits:

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilog] 8倍频vhdl

Description: 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
Platform: | Size: 1024 | Author: 罗兵武 | Hits:

[VHDL-FPGA-Verilog] pulse-VHDL

Description: 可控脉冲产生ＶＨＤＬ程序 开发软件ＩＳＥ，程序通过了器件后仿真并在芯片ＸＣ９５７２中实现了-controllable pulse generated VHDL ISE software development procedures, procedures adopted after the simulation devices and chips to achieve the XC9572
Platform: | Size: 44032 | Author: 林海 | Hits:

[VHDL-FPGA-Verilog] taxi-vhdl

Description: 出租车计费器 硬件描述语言 出租车计费器 MAX+PLUS软件 数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Platform: | Size: 48128 | Author: aneeee | Hits:

[VHDL-FPGA-Verilog] 100Examples

Description: 该源码为用VHDL（硬件描述语言）编写的100个实例的源代码，是学习VHDL的绝好资源。软件环境为maxplus10.2及以上版本或Quartus2。-The source for the use of VHDL (Hardware Description Language) preparation of the 100 examples of the source code, is an excellent resource to learn VHDL. Software environment for maxplus10.2 and above or Quartus2.
Platform: | Size: 209920 | Author: gung66 | Hits:

[Education soft system] VHDL

Description: VHDL的课件，其中包含了丰富的VHDL设计实例，是一个很好的EDA学习教程。-The VHDL software, which contains a wealth of VHDL design example, the EDA is a very good learning tutorial.
Platform: | Size: 814080 | Author: bird | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 很好的课件，有需要的朋友可以下去看下。很多比较简单的说明-Very good software, there is a need of a friend can go facie
Platform: | Size: 14308352 | Author: quanquan | Hits:

[GPS develop] A.Software.Defined.GPS.and.Galileo.Receiver

Description: Software-defined radios (SDRs) have been around for more than a decade. The first complete Global Positioning System (GPS) implementation was described by Dennis Akos in 1997. Since then several research groups have presented their contributions.We therefore find it timely to publish an up-to-date text on the subject and at the same time include Galileo, the forthcoming European satellitebased navigation system. Both GPS and Galileo belong to the category of Global Navigation Satellite Systems (GNSS)
Platform: | Size: 1932288 | Author: hamed | Hits:

[SCM] 8051-core

Description: mcu8051 CPU FPGA VHDL software
Platform: | Size: 52224 | Author: 房有定 | Hits:

[VHDL-FPGA-Verilog] vhdl-arm-core

Description: 用vhdl语言实现arm内核，压缩包中有19个代码共同组成这个arm内核，程序比较大，应用时要注意那个代码是顶层实体。用quartus2软件即可打开仿真。-Vhdl language used arm core, compressed package code of 19 common core component of this arm, procedures, and application code should be noted that top-level entity. Used to open quartus2 simulation software.
Platform: | Size: 41984 | Author: 杨帆 | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升； 当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降； 当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。 注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl译码显示器设计

Description: vhdl译码显示器设计，用quartus2软件编写，可实现数码管的显示译码功能。(VHDL decipher display design, written in quartus2 software, can realize the display and decoding function of the digital tube.)
Platform: | Size: 7680000 | Author: YXT800 | Hits:

[VHDL-FPGA-Verilog] 可逆计数器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible counter by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 12288 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] 按键去抖电路VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 29696 | Author: lixilin | Hits:
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