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[Applications] ZBT SRAM

Description: 用verilog HDL写的操作SRAM的源码-with Verilog HDL write operation SRAM FOSS
Platform: | Size: 6144 | Author: 刘波 | Hits:

[VHDL-FPGA-Verilog] cy7c1371c_vhdl_10

Description: cy7c1371c ZBT SRAM 的仿真模型，VHDL编写。-the simulate model of cy7c1371c,VHDL language.
Platform: | Size: 7168 | Author: Tangyao | Hits:

[Windows Develop] IS61WV51216

Description: iss simulation model for 512KX16 SRAM
Platform: | Size: 3072 | Author: deep | Hits:

[VHDL-FPGA-Verilog] T6_SRAM

Description:
Platform: | Size: 1547264 | Author: 汪东 | Hits:

[SCM] fpga_drive_ad7892

Description: 利用FPGA驱动12位的AD7892进行模数变换，并将数据存储到SRAM中。FPGA型号为EP1C3-144。并通过LED将12位AD值显示出来。-The use of FPGA-driven 12-bit AD7892 analog to digital conversion, and data is stored in the SRAM. FPGA model EP1C3-144. Through the LED will be 12-bit AD value is displayed.
Platform: | Size: 504832 | Author: shuaige | Hits:

[VHDL-FPGA-Verilog] IS64LV6416L

Description: Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model
Platform: | Size: 24576 | Author: veriyc | Hits:

[VHDL-FPGA-Verilog] cy7c199_10vc_vhdl_10

Description: 8位32K的SRAM防真模型，VHDL语言编写-Anti-32K of SRAM 8-bit true model, VHDL language
Platform: | Size: 3072 | Author: 王首浩 | Hits:

[VHDL-FPGA-Verilog] SRAM

Description: 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it is read and write for IS61LV24516 model, if not required for this type of SRAM timing of the program changes. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 1024 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] cy62127vll_70bai_vhdl_10

Description: SRAM CY62127DV30LL. vhdl model
Platform: | Size: 2048 | Author: frank | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram操作vhdl源程序，内有sdram模型，控制器设计，及测试源程序-sram operating in vhdl \doc DDR SDRAM reference design documentation \model Contains the vhdl SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the vhdl testbench, modelsim project file, and library \source Contains the vhdl source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 897024 | Author: chen | Hits:

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