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[Other resource] VHDL-status

Description: VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Platform: | Size: 6465 | Author: 陈度甫 | Hits:

[VHDL-FPGA-Verilog] State.Machine

Description: State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
Platform: | Size: 123904 | Author: | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使用select语句） LED七段译码 多路选择器（使用if－else语句） 双2－4译码器：74139 多路选择器（使用when－else语句） 二进制到BCD码转换 多路选择器 （使用case语句） 二进制到格雷码转换 双向总线（注2） 汉明纠错吗译码器 三态总线（注2） 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] vhdl程序例子

Description: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Platform: | Size: 168960 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] 状态机设计

Description: 详细说明状态机的设计，用VHDL实现，是不错的教程-detailed state machine design, VHDL, is a good guide
Platform: | Size: 113664 | Author: wl | Hits:

[VHDL-FPGA-Verilog] 66vhdl_src

Description: 66个vhdl的常用源代码，包括有双向口、状态机等，自解压后看vhdl_example.html列表说明.exe-66 vhdl common source code, including the two-mouth state machine, Since unpacked see vhdl_example.html tabulated. exe
Platform: | Size: 98304 | Author: 刘丙周 | Hits:

[VHDL-FPGA-Verilog] VHDL-status

Description: VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Platform: | Size: 6144 | Author: 陈度甫 | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[Software Engineering] VHDL

Description: 基才VHDL状态机设计的智能交通控制灯 设计 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to design can look at the
Platform: | Size: 139264 | Author: 杨树茂 | Hits:

[Books] VHDL

Description: 基才VHDL状态机设计的智能交通控制灯 有需要的可以看一下-only VHDL-based state machine design and intelligent traffic control lights need to see what
Platform: | Size: 261120 | Author: 杨树茂 | Hits:

[Software Engineering] State-Machi-ne-Coding-Styles-for-Synthesis

Description: 国外论文，超经典的状态机描述，学习vhdl必看-International Paper, ultra classic state machine description, learning VHDL must-see
Platform: | Size: 123904 | Author: 行卡 | Hits:

[Other] state

Description: 状态机设计的vhdl源程序及文章pdf,欢迎交流.-State machine VHDL design source code and article pdf, welcomed the exchange.
Platform: | Size: 157696 | Author: 大鲁 | Hits:

[Software Engineering] State

Description: 状态机资料,状态机是FPGA设计的常用方法,资源多多共享,不亦乐乎!-State machine data, state machine is a common method for FPGA design, resources, a lot of sharing, joy!
Platform: | Size: 589824 | Author: wangzhe | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[Books] 7_4617

Description: VHDL状态机设计，如何设计一个可以通用的状态机，如何保证状态机的可维护性和可扩展性。-VHDL state machine design, how to design a generic state machine, how to ensure that state machine maintainability and scalability.
Platform: | Size: 114688 | Author: IvanYang | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于VHDL状态机设计的智能交通控制灯VHDL程序-VHDL-based state machine design of intelligent traffic control lights VHDL procedures
Platform: | Size: 285696 | Author: 徐翔 | Hits:

[VHDL-FPGA-Verilog] delay

Description: 用vhdl的状态机实现精确的1us的延时程序-VHDL state machine used to achieve precise 1us delay procedures
Platform: | Size: 1024 | Author: yim | Hits:

[VHDL-FPGA-Verilog] State-Machine

Description: 这是个人整理的11篇有关状态机的资料，很有用。-This is a personal order of 11 information on the state machine, very useful.
Platform: | Size: 3501056 | Author: 郑生 | Hits:

[SCM] State Machine

Description: VHDL State machine code
Platform: | Size: 1385472 | Author: Tokyosn1 | Hits:
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