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[Other resource] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。
Platform: | Size: 6262 | Author: sxd | Hits:

[Other resource] VHDL-timer

Description: 这是关于VHDL时钟的源代码，欢迎大家下载交流！
Platform: | Size: 6967 | Author: 张三 | Hits:

[Other] ptc

Description: PWM/TIMER/COUNTER VHDL IP core
Platform: | Size: 272384 | Author: hehilon | Hits:

[Software Engineering] DigitalssStopwatch

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1/100 seconds timer control and all the regular functions, its small size and easy to carry.
Platform: | Size: 7168 | Author: 段苛苛 | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[ARM-PowerPC-ColdFire-MIPS] VHDL-timer

Description: 这是关于VHDL时钟的源代码，欢迎大家下载交流！-This is a clock on the VHDL source code, welcomed the exchange of everyone to download!
Platform: | Size: 7168 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能-Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions
Platform: | Size: 349184 | Author: gz208 | Hits:

[VHDL-FPGA-Verilog] mc_8051

Description: 该源代码是实现了8051 mcu core的VHDL代码，中断、计时等各功能全面，且包括了各部分的详细测试文件-The source code is to achieve a 8051 mcu core of the VHDL code, interrupt, timer and other full-featured, and includes details of the various parts of the test document
Platform: | Size: 657408 | Author: swelgan | Hits:

[Software Engineering] CPLD-timer

Description: 本文介绍一种以CPLD[1]为核心、以VHDL[2]为开发工具的时间控制器，该控制器不仅具有时间功能，而且具有定时器功能，能在00：00～23：59之间任意设定开启时间和关闭时间，其设置方便、灵活，广泛应用于路灯、广告灯箱、霓虹灯等处的定时控制。-This article describes a CPLD [1] as the core, VHDL [2] for the development of tools for time controller that features not only has the time, but with the timer function, can be between 00:00 ~ 23:59 arbitrarily set to open time and closing time, and its convenient, flexible, widely used in street lamps, advertising light boxes, neon lights, etc. The timing control.
Platform: | Size: 219136 | Author: 江俊 | Hits:

[VHDL-FPGA-Verilog] timer

Description: vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
Platform: | Size: 59392 | Author: daxiadian2 | Hits:

[VHDL-FPGA-Verilog] FPGA_jiaocheng_yu_shiyan

Description: 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three experiments _SOPC_LED programmer _Flash the basis of four experiments of five experiments _ timer six experimental basis _ keys, as well as experimental experimental PIO interrupt I _ 7 card use, these laboratories used the SOPC BUILDER with NOIS ii, the use of Verilog to prepare, there are no experimental test panels and plates can be used to learn. The second also includes: FPGA development board of the links between memory, multi-processor documents, USB_UART such as documents, useful documents, you will not regret it a sure!
Platform: | Size: 6065152 | Author: yuezhiying_007 | Hits:

[VHDL-FPGA-Verilog] timer

Description: VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
Platform: | Size: 1024 | Author: 孙明 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Platform: | Size: 1024 | Author: 劉季泓 | Hits:

[Documents] vhdl

Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: | Size: 4096 | Author: 王睿 | Hits:

[VHDL-FPGA-Verilog] gh_timer_8254

Description: VHDL Source code for 8254 timer/counter
Platform: | Size: 106496 | Author: Alireza | Hits:

[VHDL-FPGA-Verilog] gh_vhdl_lib

Description: VHDL Library for 8254 timer/counter core
Platform: | Size: 627712 | Author: Alireza | Hits:

[VHDL-FPGA-Verilog] Timer

Description: ep2c5 实现 定时器 verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
Platform: | Size: 497664 | Author: lizhuodong | Hits:

[VHDL-FPGA-Verilog] timer

Description: 计时器的Verilog描述 CPU设计者可以借鉴 -Verilog decription of the timer in processors
Platform: | Size: 2048 | Author: Dee | Hits:

[Internet-Network] timer

Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
Platform: | Size: 1024 | Author: kkris | Hits:

[VHDL-FPGA-Verilog] timer

Description: 外设timer设计：16bit定时器、ETU计数器、具有3种可配置中断请求输出、内部寄存器的读写编程。-Peripheral timer design: 16bit timer, ETU counter, with 3 configurable interrupt request output, the internal register read and write programming.
Platform: | Size: 5120 | Author: gab | Hits:
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