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[Other resource] Exp4-Clock

Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
Platform: | Size: 808948 | Author: 萧飒 | Hits:

[VHDL-FPGA-Verilog] 多功能电子钟

Description: 具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Platform: | Size: 6144 | Author: 张建 | Hits:

[VHDL-FPGA-Verilog] Exp4-Clock

Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
Platform: | Size: 808960 | Author: 萧飒 | Hits:

[VHDL-FPGA-Verilog] byvhdstopwatchl

Description: 1.高精度数字秒表（0.01秒的vhdl语言实现） 2.具有定时，暂停，按键随机存储，翻页回放功能； 3.对30M时钟分频产生显示扫描时钟 4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。 5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design)
Platform: | Size: 2048 | Author: 方周 | Hits:

[Software Engineering] DigitalssStopwatch

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1/100 seconds timer control and all the regular functions, its small size and easy to carry.
Platform: | Size: 7168 | Author: 段苛苛 | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[ARM-PowerPC-ColdFire-MIPS] VHDL-timer

Description: 这是关于VHDL时钟的源代码，欢迎大家下载交流！-This is a clock on the VHDL source code, welcomed the exchange of everyone to download!
Platform: | Size: 7168 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 1、正常的计时功能：即具有二十四小时计时功能 2、正常的显示功能 3、正常的调时功能 4、闹钟定时功能 5、整点报时功能 -1, the normal timing functions: that is, with 24 hours timer function 2, the normal display 3, the normal transfer function 4 hours, alarm clock timer 5, the whole point timekeeping function
Platform: | Size: 505856 | Author: 杨雄 | Hits:

[assembly language] clock

Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
Platform: | Size: 11264 | Author: 金珊珊 | Hits:

[VHDL-FPGA-Verilog] timer

Description: vhdl代码：电子时钟VHDL程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: electronic clock and simulation of VHDL procedures! FPGA beginner who can refer to reference! ! Relatively simple
Platform: | Size: 59392 | Author: daxiadian2 | Hits:

[OS program] Timer

Description: 基于ｖｈｄｌ的电子时钟，其中包括六进制计数器和十进制计数器。-VHDL-based electronic clock, including six hexadecimal decimal counters and counters.
Platform: | Size: 110592 | Author: kathy | Hits:

[VHDL-FPGA-Verilog] timer

Description: VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs
Platform: | Size: 1024 | Author: 孙明 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
Platform: | Size: 1024 | Author: 劉季泓 | Hits:

[Documents] vhdl

Description: 6位LED电子钟,非常实用实做过实验，自动报时，秒表-6 LED electronic clock, very useful experiment is done, automatic timer, stopwatch. . .
Platform: | Size: 4096 | Author: 王睿 | Hits:

[VHDL-FPGA-Verilog] FPGA_Clk

Description: 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other modules. The use of the timer-generated clock waveform. To provide for the FPGA clock even sub-frequency, odd-numbered sub-frequency, pulse width is always functions.
Platform: | Size: 1466368 | Author: icemoon1987 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 基于VHDL语言，实现时钟功能，显示时间从00：00：00到23：59：59，并将其输出信号转换为数码管信号-Based on the VHDL language, to achieve the clock function, display time from 00:00:00 to 23:59:59, and the output signal is converted to digital control signals
Platform: | Size: 498688 | Author: 陈伟 | Hits:

[VHDL-FPGA-Verilog] timer

Description: 这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function.
Platform: | Size: 791552 | Author: 紫郢寒光 | Hits:

[Embeded-SCM Develop] DigitalClock

Description: 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results.
Platform: | Size: 63488 | Author: sunnan | Hits:

[VHDL-FPGA-Verilog] shuzizhong_VHDL

Description: 用VHDL语言写了数字钟程序，并用数码管显示，经过硬件调试可行-timer clock
Platform: | Size: 640000 | Author: cc | Hits:

[VHDL-FPGA-Verilog] clock

Description: 基于vhdl的数字时钟，可以定时报警，可以调分钟，小时-Based vhdl digital clock, timer alarm, you can tune in minutes, hours
Platform: | Size: 1157120 | Author: songlinzhan | Hits:
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